[PATCH] D16434: Fix ARM load/store opt live reg computing

[Weiming Zhao via llvm-commits]

weimingz added a comment.

  E.g.:
  Before LD/ST opt:
  BB1:
    ...
    %SP<def,tied1> = t2LDMIA_UPD %SP<tied0>, pred:14, pred:%noreg,
                     %R4<def>, %R5<def>, %R7<def>, %LR<def>
    Successors according to CFG: BB#3
  
  BB#3: derived from LLVM BB %if.end
      Live Ins: %R0 %R1 %R2 %R3 %R12 %LR %R7 %R5 %R4
      t2STRi12 %R2<kill>, %R1, 20, pred:14, pred:%noreg;
      t2STRi12 %R3<kill>, %R1, 24, pred:14, pred:%noreg; mem:ST4[%22]
      t2STRi12 %R12<kill>, %R1, 28, pred:14, pred:%noreg; mem:ST4[%23]
      tBX_RET pred:14, pred:%noreg
  
  After LD/ST opt:
  BB#3: derived from LLVM BB %if.end
      Live Ins: %R0 %R1 %R2 %R3 %R12 %LR %R7 %R5 %R4
      %LR<def> = t2ADDri %R1, 20, pred:14, pred:%noreg, opt:%noreg
      t2STMIA %LR<kill>, pred:14, pred:%noreg, %R2<kill>, %R3<kill>, %R12<kill>
      tBX_RET pred:14, pred:%noreg


Repository:
  rL LLVM

http://reviews.llvm.org/D16434