[llvm] r258419 - [TTI] Add getCacheLineSize
Adam Nemet via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 21 10:28:37 PST 2016
Author: anemet
Date: Thu Jan 21 12:28:36 2016
New Revision: 258419
URL: http://llvm.org/viewvc/llvm-project?rev=258419&view=rev
Log:
[TTI] Add getCacheLineSize
Summary:
And use it in PPCLoopDataPrefetch.cpp.
@hfinkel, please let me know if your preference would be to preserve the
ppc-loop-prefetch-cache-line option in order to be able to override the
value of TTI::getCacheLineSize for PPC.
Reviewers: hfinkel
Subscribers: hulx2000, mcrosier, mssimpso, hfinkel, llvm-commits
Differential Revision: http://reviews.llvm.org/D16306
Modified:
llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h
llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/trunk/lib/Analysis/TargetTransformInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h
Modified: llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h?rev=258419&r1=258418&r2=258419&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h Thu Jan 21 12:28:36 2016
@@ -416,6 +416,9 @@ public:
/// \return The width of the largest scalar or vector register type.
unsigned getRegisterBitWidth(bool Vector) const;
+ /// \return The size of a cache line in bytes.
+ unsigned getCacheLineSize() const;
+
/// \return The maximum interleave factor that any transform should try to
/// perform for this target. This number depends on the level of parallelism
/// and the number of execution units in the CPU.
@@ -609,6 +612,7 @@ public:
Type *Ty) = 0;
virtual unsigned getNumberOfRegisters(bool Vector) = 0;
virtual unsigned getRegisterBitWidth(bool Vector) = 0;
+ virtual unsigned getCacheLineSize() = 0;
virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
virtual unsigned
getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
@@ -775,6 +779,9 @@ public:
unsigned getRegisterBitWidth(bool Vector) override {
return Impl.getRegisterBitWidth(Vector);
}
+ unsigned getCacheLineSize() override {
+ return Impl.getCacheLineSize();
+ }
unsigned getMaxInterleaveFactor(unsigned VF) override {
return Impl.getMaxInterleaveFactor(VF);
}
Modified: llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h?rev=258419&r1=258418&r2=258419&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h (original)
+++ llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h Thu Jan 21 12:28:36 2016
@@ -264,6 +264,8 @@ public:
unsigned getRegisterBitWidth(bool Vector) { return 32; }
+ unsigned getCacheLineSize() { return 0; }
+
unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
Modified: llvm/trunk/lib/Analysis/TargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TargetTransformInfo.cpp?rev=258419&r1=258418&r2=258419&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/TargetTransformInfo.cpp Thu Jan 21 12:28:36 2016
@@ -215,6 +215,10 @@ unsigned TargetTransformInfo::getRegiste
return TTIImpl->getRegisterBitWidth(Vector);
}
+unsigned TargetTransformInfo::getCacheLineSize() const {
+ return TTIImpl->getCacheLineSize();
+}
+
unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
return TTIImpl->getMaxInterleaveFactor(VF);
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp?rev=258419&r1=258418&r2=258419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp Thu Jan 21 12:28:36 2016
@@ -50,10 +50,6 @@ static cl::opt<unsigned>
PrefDist("ppc-loop-prefetch-distance", cl::Hidden, cl::init(300),
cl::desc("The loop prefetch distance"));
-static cl::opt<unsigned>
-CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
- cl::desc("The loop prefetch cache line size"));
-
namespace llvm {
void initializePPCLoopDataPrefetchPass(PassRegistry&);
}
@@ -110,6 +106,8 @@ bool PPCLoopDataPrefetch::runOnFunction(
AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+ assert(TTI->getCacheLineSize() && "Cache line size is not set for target");
+
bool MadeChange = false;
for (auto I = LI->begin(), IE = LI->end(); I != IE; ++I)
@@ -193,7 +191,7 @@ bool PPCLoopDataPrefetch::runOnLoop(Loop
if (const SCEVConstant *ConstPtrDiff =
dyn_cast<SCEVConstant>(PtrDiff)) {
int64_t PD = std::abs(ConstPtrDiff->getValue()->getSExtValue());
- if (PD < (int64_t) CacheLineSize) {
+ if (PD < (int64_t) TTI->getCacheLineSize()) {
DupPref = true;
break;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp?rev=258419&r1=258418&r2=258419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp Thu Jan 21 12:28:36 2016
@@ -21,6 +21,12 @@ using namespace llvm;
static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
+// This is currently only used for the data prefetch pass which is only enabled
+// for BG/Q by default.
+static cl::opt<unsigned>
+CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
+ cl::desc("The loop prefetch cache line size"));
+
//===----------------------------------------------------------------------===//
//
// PPC cost model.
@@ -230,6 +236,12 @@ unsigned PPCTTIImpl::getRegisterBitWidth
}
+unsigned PPCTTIImpl::getCacheLineSize() {
+ // This is currently only used for the data prefetch pass which is only
+ // enabled for BG/Q by default.
+ return CacheLineSize;
+}
+
unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
unsigned Directive = ST->getDarwinDirective();
// The 440 has no SIMD support, but floating-point instructions
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h?rev=258419&r1=258418&r2=258419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h Thu Jan 21 12:28:36 2016
@@ -70,6 +70,7 @@ public:
bool enableInterleavedAccessVectorization();
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
+ unsigned getCacheLineSize();
unsigned getMaxInterleaveFactor(unsigned VF);
int getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
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