[PATCH] D16291: AArch64: Implement missed conditional compare sequences.
Chad Rosier via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 21 06:48:20 PST 2016
mcrosier added inline comments.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1566
@@ +1565,3 @@
+ bool canPushNegate;
+ if (!(isConjunctionDisjunctionTree(LHS, canPushNegate)))
+ return SDValue();
----------------
No need for the extra parens around the call is isConjunctionDisjunctionTree.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1568
@@ +1567,3 @@
+ return SDValue();
+ if (!(isConjunctionDisjunctionTree(RHS, canPushNegate)))
+ return SDValue();
----------------
Same; No need for the extra parens around the call is isConjunctionDisjunctionTree.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1570
@@ +1569,3 @@
+ return SDValue();
+ if ((LHS.getOpcode() != ISD::SETCC) || (RHS.getOpcode() != ISD::SETCC))
+ return Op;
----------------
If possible, I would hoist this check above the calls to isConjunctionDisjunctionTree.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1702
@@ +1701,3 @@
+SDValue AArch64TargetLowering::LowerAND(SDValue Op, SelectionDAG &DAG) const {
+
+ if (Op.getValueType().isVector())
----------------
Please remove the extra whitespace.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1710
@@ +1709,3 @@
+SDValue AArch64TargetLowering::LowerOR(SDValue Op, SelectionDAG &DAG) const {
+
+ if (Op.getValueType().isVector())
----------------
Please remove the extra whitespace.
http://reviews.llvm.org/D16291
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