[llvm] r258352 - AMDGPU/SI: Promote i1 SETCC operations
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 20 13:48:24 PST 2016
Author: tstellar
Date: Wed Jan 20 15:48:24 2016
New Revision: 258352
URL: http://llvm.org/viewvc/llvm-project?rev=258352&view=rev
Log:
AMDGPU/SI: Promote i1 SETCC operations
Summary:
While working on uniform branching, I've hit a few cases where we emit
i1 SETCC operations.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D16233
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/test/CodeGen/AMDGPU/setcc.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=258352&r1=258351&r2=258352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Wed Jan 20 15:48:24 2016
@@ -103,6 +103,7 @@ SITargetLowering::SITargetLowering(Targe
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
+ setOperationAction(ISD::SETCC, MVT::i1, Promote);
setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
Modified: llvm/trunk/test/CodeGen/AMDGPU/setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/setcc.ll?rev=258352&r1=258351&r2=258352&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/setcc.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/setcc.ll Wed Jan 20 15:48:24 2016
@@ -389,3 +389,23 @@ if:
endif:
ret void
}
+
+; FUNC-LABEL: setcc-i1-and-xor
+; SI-DAG: v_cmp_le_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
+; SI-DAG: v_cmp_ge_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], 1.0, s{{[0-9]+}}
+; SI: s_and_b64 s[2:3], [[A]], [[B]]
+define void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 {
+bb0:
+ %tmp5 = fcmp oge float %cond, 0.000000e+00
+ %tmp7 = fcmp ole float %cond, 1.000000e+00
+ %tmp9 = and i1 %tmp5, %tmp7
+ %tmp11 = xor i1 %tmp9, 1
+ br i1 %tmp11, label %bb2, label %bb1
+
+bb1:
+ store i32 0, i32 addrspace(1)* %out
+ br label %bb2
+
+bb2:
+ ret void
+}
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