[PATCH] D16291: AArch64: Implement missed conditional compare sequences.

[Balaram Makam via llvm-commits]

bmakam added a comment.

Thanks for the feedback Matthias and Geoff,

The approach here is to catch the cases where LowerSELECT failed to construct ccmp sequences, so had to be done at LowerOR/LowerAND. The current patch fails to catch the cases mentioned by Geoff because of the restriction to Return inputs. We should be able to handle other than returns and I was saving this for a follow on patch because it breaks the select_noccmp1 test case in arm64-ccmp.ll:

  define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
    %c0 = icmp slt i64 %v1, 0
    %c1 = icmp sgt i64 %v1, 13
    %c2 = icmp slt i64 %v3, 2
    %c4 = icmp sgt i64 %v3, 4
    %and0 = and i1 %c0, %c1
    %and1 = and i1 %c2, %c4
    %or = or i1 %and0, %and1
    %sel = select i1 %or, i64 0, i64 %r
    ret i64 %sel
  }

Matthias, can you please let know why you added this test case? I think we fail to construct ccmp sequence here because the tree at or i1 is not a conjunctiondisjunction tree as we cannot push negate operation through the tree not (or (and x y) (and x z)). However, with the current approach of doing the transformation at LowerOR/LowerAND we can look at the sub-trees (and x y), (and x z) respectively and they can be transformed into ccmp sequences thus breaking this testcase. Is it reasonable to modify the test case if we agree on extending this to catch the cases Geoff mentioned?


http://reviews.llvm.org/D16291