[llvm] r258085 - AMDGPU: Add subtarget feature for instruction rates
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 18 13:13:50 PST 2016
Author: arsenm
Date: Mon Jan 18 15:13:50 2016
New Revision: 258085
URL: http://llvm.org/viewvc/llvm-project?rev=258085&view=rev
Log:
AMDGPU: Add subtarget feature for instruction rates
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/Processors.td
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=258085&r1=258084&r2=258085&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Mon Jan 18 15:13:50 2016
@@ -59,6 +59,12 @@ def FeatureFastFMAF32 : SubtargetFeature
"Assuming f32 fma is at least as fast as mul + add",
[]>;
+def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
+ "HalfRate64Ops",
+ "true",
+ "Most fp64 instructions are half rate instead of quarter",
+ []>;
+
// Some instructions do not support denormals despite this flag. Using
// fp32 denormals also causes instructions to run at the double
// precision rate for the device.
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=258085&r1=258084&r2=258085&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Mon Jan 18 15:13:50 2016
@@ -70,11 +70,14 @@ AMDGPUSubtarget::AMDGPUSubtarget(const T
DumpCode(false), R600ALUInst(false), HasVertexCache(false),
TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
- CaymanISA(false), FlatAddressSpace(false), FlatForGlobal(false),
- EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
- EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
+ HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false),
+ FlatForGlobal(false), EnableIRStructurizer(true),
+ EnablePromoteAlloca(false),
+ EnableIfCvt(true), EnableLoadStoreOpt(false),
+ EnableUnsafeDSOffsetFolding(false),
EnableXNACK(false),
- WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
+ WavefrontSize(0), CFALUBug(false),
+ LocalMemorySize(0),
EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=258085&r1=258084&r2=258085&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Mon Jan 18 15:13:50 2016
@@ -69,6 +69,7 @@ private:
bool FP64Denormals;
bool FP32Denormals;
bool FastFMAF32;
+ bool HalfRate64Ops;
bool CaymanISA;
bool FlatAddressSpace;
bool FlatForGlobal;
@@ -158,6 +159,10 @@ public:
return FastFMAF32;
}
+ bool hasHalfRate64Ops() const {
+ return HalfRate64Ops;
+ }
+
bool hasFlatAddressSpace() const {
return FlatAddressSpace;
}
Modified: llvm/trunk/lib/Target/AMDGPU/Processors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Processors.td?rev=258085&r1=258084&r2=258085&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Processors.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/Processors.td Mon Jan 18 15:13:50 2016
@@ -84,11 +84,11 @@ def : Proc<"cayman", R600_VLIW4_Itin
//===----------------------------------------------------------------------===//
def : ProcessorModel<"SI", SIFullSpeedModel,
- [FeatureSouthernIslands, FeatureFastFMAF32]
+ [FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
>;
-def : ProcessorModel<"tahiti", SIFullSpeedModel,
- [FeatureSouthernIslands, FeatureFastFMAF32]
+def : ProcessorModel<"tahiti", SIFullSpeedModel,
+ [FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
>;
def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
@@ -116,8 +116,8 @@ def : ProcessorModel<"kaveri", SIQua
>;
def : ProcessorModel<"hawaii", SIFullSpeedModel,
- [FeatureSeaIslands, FeatureFastFMAF32, FeatureLDSBankCount32,
- FeatureISAVersion7_0_1]
+ [FeatureSeaIslands, FeatureFastFMAF32, HalfRate64Ops,
+ FeatureLDSBankCount32, FeatureISAVersion7_0_1]
>;
def : ProcessorModel<"mullins", SIQuarterSpeedModel,
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