[llvm] r257995 - [X86][AVX] Regenerated AVX tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 16 07:25:03 PST 2016
Author: rksimon
Date: Sat Jan 16 09:25:02 2016
New Revision: 257995
URL: http://llvm.org/viewvc/llvm-project?rev=257995&view=rev
Log:
[X86][AVX] Regenerated AVX tests
Updated i1 select, vector truncation and subvector extraction tests
Modified:
llvm/trunk/test/CodeGen/X86/avx-select.ll
llvm/trunk/test/CodeGen/X86/avx-trunc.ll
llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll
Modified: llvm/trunk/test/CodeGen/X86/avx-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-select.ll?rev=257995&r1=257994&r2=257995&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-select.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-select.ll Sat Jan 16 09:25:02 2016
@@ -1,19 +1,34 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
-; CHECK: _select00
-; CHECK: vmovaps
-; CHECK-NEXT: LBB
define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: select00:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: cmpl $255, %edi
+; CHECK-NEXT: je LBB0_2
+; CHECK-NEXT: ## BB#1:
+; CHECK-NEXT: vmovaps %ymm0, %ymm1
+; CHECK-NEXT: LBB0_2:
+; CHECK-NEXT: vxorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
%cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <8 x i32> zeroinitializer, <8 x i32> %b
%res = xor <8 x i32> %b, %selres
ret <8 x i32> %res
}
-; CHECK: _select01
-; CHECK: vmovaps
-; CHECK-NEXT: LBB
define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
+; CHECK-LABEL: select01:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: cmpl $255, %edi
+; CHECK-NEXT: je LBB1_2
+; CHECK-NEXT: ## BB#1:
+; CHECK-NEXT: vmovaps %ymm0, %ymm1
+; CHECK-NEXT: LBB1_2:
+; CHECK-NEXT: vxorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
%cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <4 x i64> zeroinitializer, <4 x i64> %b
%res = xor <4 x i64> %b, %selres
Modified: llvm/trunk/test/CodeGen/X86/avx-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-trunc.ll?rev=257995&r1=257994&r2=257995&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-trunc.ll Sat Jan 16 09:25:02 2016
@@ -1,22 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
define <4 x i32> @trunc_64_32(<4 x i64> %A) nounwind uwtable readnone ssp{
-; CHECK-LABEL: trunc_64_32
-; CHECK: pshufd
-; CHECK: pshufd
-; CHECK: pblendw
+; CHECK-LABEL: trunc_64_32:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
+; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
%B = trunc <4 x i64> %A to <4 x i32>
ret <4 x i32>%B
}
+
define <8 x i16> @trunc_32_16(<8 x i32> %A) nounwind uwtable readnone ssp{
-; CHECK-LABEL: trunc_32_16
-; CHECK: pshufb
+; CHECK-LABEL: trunc_32_16:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
%B = trunc <8 x i32> %A to <8 x i16>
ret <8 x i16>%B
}
+
define <16 x i8> @trunc_16_8(<16 x i16> %A) nounwind uwtable readnone ssp{
-; CHECK-LABEL: trunc_16_8
-; CHECK: pshufb
+; CHECK-LABEL: trunc_16_8:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
%B = trunc <16 x i16> %A to <16 x i8>
ret <16 x i8> %B
}
Modified: llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll?rev=257995&r1=257994&r2=257995&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll Sat Jan 16 09:25:02 2016
@@ -1,28 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
-; CHECK-LABEL: A:
-; CHECK-NOT: vunpck
-; CHECK: vextractf128 $1
define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
+; CHECK-LABEL: A:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: retq
entry:
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8>
ret <8 x float> %shuffle
}
-; CHECK-LABEL: B:
-; CHECK-NOT: vunpck
-; CHECK: vextractf128 $1
define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
+; CHECK-LABEL: B:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: retq
entry:
%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
ret <4 x double> %shuffle
}
-; CHECK-LABEL: t0:
-; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NOT: vmovaps %xmm0, (%rdi)
-; CHECK: vextractf128 $1, %ymm0, (%rdi)
define void @t0(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t0:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vextractf128 $1, %ymm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 1)
%1 = bitcast float* %addr to <4 x float>*
@@ -30,13 +34,12 @@ entry:
ret void
}
-declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
-
-; CHECK-LABEL: t2:
-; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NOT: vmovaps %xmm0, (%rdi)
-; CHECK: vextractf128 $1, %ymm0, (%rdi)
define void @t2(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t2:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vextractf128 $1, %ymm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 1)
%1 = bitcast double* %addr to <2 x double>*
@@ -44,13 +47,12 @@ entry:
ret void
}
-declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
-
-; CHECK-LABEL: t4:
-; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NOT: vmovaps %xmm0, (%rdi)
-; CHECK: vextractf128 $1, %ymm0, (%rdi)
define void @t4(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t4:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vextractf128 $1, %ymm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = bitcast <4 x i64> %a to <8 x i32>
%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 1)
@@ -59,11 +61,12 @@ entry:
ret void
}
-declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
-
-; CHECK-LABEL: t5:
-; CHECK: vmovaps %xmm0, (%rdi)
define void @t5(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t5:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vmovaps %xmm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0)
%1 = bitcast float* %addr to <4 x float>*
@@ -71,9 +74,12 @@ entry:
ret void
}
-; CHECK-LABEL: t6:
-; CHECK: vmovaps %xmm0, (%rdi)
define void @t6(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t6:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vmovaps %xmm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0)
%1 = bitcast double* %addr to <2 x double>*
@@ -81,9 +87,12 @@ entry:
ret void
}
-; CHECK-LABEL: t7:
-; CHECK: vmovaps %xmm0, (%rdi)
define void @t7(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t7:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vmovaps %xmm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = bitcast <4 x i64> %a to <8 x i32>
%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
@@ -92,9 +101,12 @@ entry:
ret void
}
-; CHECK-LABEL: t8:
-; CHECK: vmovups %xmm0, (%rdi)
define void @t8(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
+; CHECK-LABEL: t8:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: vmovups %xmm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
%0 = bitcast <4 x i64> %a to <8 x i32>
%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
@@ -105,6 +117,12 @@ entry:
; PR15462
define void @t9(i64* %p) {
+; CHECK-LABEL: t9:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovups %ymm0, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
store i64 0, i64* %p
%q = getelementptr i64, i64* %p, i64 1
store i64 0, i64* %q
@@ -113,9 +131,8 @@ define void @t9(i64* %p) {
%s = getelementptr i64, i64* %p, i64 3
store i64 0, i64* %s
ret void
-
-; CHECK-LABEL: t9:
-; CHECK: vxorps %xmm
-; CHECK-NOT: vextractf
-; CHECK: vmovups
}
+
+declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
+declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
+declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
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