[llvm] r257916 - # This is a combination of 2 commits.
Reid Kleckner via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 15 10:31:30 PST 2016
Author: rnk
Date: Fri Jan 15 12:31:29 2016
New Revision: 257916
URL: http://llvm.org/viewvc/llvm-project?rev=257916&view=rev
Log:
# This is a combination of 2 commits.
# The first commit's message is:
Revert "[ARM] Add DSP build attribute and extension targeting"
This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc.
# This is the 2nd commit message:
Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline"
This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5.
Removed:
llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll
llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll
llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt
Modified:
llvm/trunk/include/llvm/Support/ARMBuildAttributes.h
llvm/trunk/include/llvm/Support/ARMTargetParser.def
llvm/trunk/lib/Support/ARMBuildAttrs.cpp
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s
llvm/trunk/test/CodeGen/ARM/build-attributes.ll
llvm/trunk/test/MC/ARM/directive-eabi_attribute.s
llvm/trunk/test/MC/ARM/thumbv8m.s
llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s
llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s
llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp
llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h
Modified: llvm/trunk/include/llvm/Support/ARMBuildAttributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMBuildAttributes.h?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMBuildAttributes.h (original)
+++ llvm/trunk/include/llvm/Support/ARMBuildAttributes.h Fri Jan 15 12:31:29 2016
@@ -67,7 +67,6 @@ enum AttrType {
ABI_FP_16bit_format = 38,
MPextension_use = 42, // recoded from 70 (ABI r2.08)
DIV_use = 44,
- DSP_extension = 46,
also_compatible_with = 65,
conformance = 67,
Virtualization_use = 68,
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Fri Jan 15 12:31:29 2016
@@ -116,7 +116,6 @@ ARM_ARCH_EXT_NAME("invalid", AEK_INVALI
ARM_ARCH_EXT_NAME("none", AEK_NONE, nullptr, nullptr)
ARM_ARCH_EXT_NAME("crc", AEK_CRC, "+crc", "-crc")
ARM_ARCH_EXT_NAME("crypto", AEK_CRYPTO, "+crypto","-crypto")
-ARM_ARCH_EXT_NAME("dsp", AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", AEK_FP, nullptr, nullptr)
ARM_ARCH_EXT_NAME("idiv", (AEK_HWDIVARM | AEK_HWDIV), nullptr, nullptr)
ARM_ARCH_EXT_NAME("mp", AEK_MP, nullptr, nullptr)
Modified: llvm/trunk/lib/Support/ARMBuildAttrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ARMBuildAttrs.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/lib/Support/ARMBuildAttrs.cpp (original)
+++ llvm/trunk/lib/Support/ARMBuildAttrs.cpp Fri Jan 15 12:31:29 2016
@@ -54,7 +54,6 @@ const struct {
{ ARMBuildAttrs::ABI_FP_16bit_format, "Tag_ABI_FP_16bit_format" },
{ ARMBuildAttrs::MPextension_use, "Tag_MPextension_use" },
{ ARMBuildAttrs::DIV_use, "Tag_DIV_use" },
- { ARMBuildAttrs::DSP_extension, "Tag_DSP_extension" },
{ ARMBuildAttrs::nodefaults, "Tag_nodefaults" },
{ ARMBuildAttrs::also_compatible_with, "Tag_also_compatible_with" },
{ ARMBuildAttrs::T2EE_use, "Tag_T2EE_use" },
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jan 15 12:31:29 2016
@@ -807,9 +807,6 @@ void ARMAsmPrinter::emitAttributes() {
if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
- if (STI.hasDSP() && isV8M(&STI))
- ATS.emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
-
if (MMI) {
if (const Module *SourceModule = MMI->getModule()) {
// ABI_PCS_wchar_t to indicate wchar_t width
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jan 15 12:31:29 2016
@@ -3444,9 +3444,6 @@ static inline int getMClassRegisterSYSmV
.Case("basepri_max", 0x12)
.Case("faultmask", 0x13)
.Case("control", 0x14)
- .Case("msplim", 0x0a)
- .Case("psplim", 0x0b)
- .Case("sp", 0x18)
.Default(-1);
}
@@ -3476,27 +3473,11 @@ static int getMClassRegisterMask(StringR
if (!Subtarget->hasV7Ops() && SYSmvalue >= 0x11 && SYSmvalue <= 0x13)
return -1;
- if (Subtarget->has8MSecExt() && Flags.lower() == "ns") {
- Flags = "";
- SYSmvalue |= 0x80;
- }
-
- if (!Subtarget->has8MSecExt() &&
- (SYSmvalue == 0xa || SYSmvalue == 0xb || SYSmvalue > 0x14))
- return -1;
-
- if (!Subtarget->hasV8MMainlineOps() &&
- (SYSmvalue == 0x8a || SYSmvalue == 0x8b || SYSmvalue == 0x91 ||
- SYSmvalue == 0x93))
- return -1;
-
// If it was a read then we won't be expecting flags and so at this point
// we can return the mask.
if (IsRead) {
- if (Flags.empty())
- return SYSmvalue;
- else
- return -1;
+ assert (Flags.empty() && "Unexpected flags for reading M class register.");
+ return SYSmvalue;
}
// We know we are now handling a write so need to get the mask for the flags.
@@ -3655,13 +3636,7 @@ SDNode *ARMDAGToDAGISel::SelectReadRegis
// is an acceptable value, so check that a mask can be constructed from the
// string.
if (Subtarget->isMClass()) {
- StringRef Flags = "", Reg = SpecialReg;
- if (Reg.endswith("_ns")) {
- Flags = "ns";
- Reg = Reg.drop_back(3);
- }
-
- int SYSmValue = getMClassRegisterMask(Reg, Flags, true, Subtarget);
+ int SYSmValue = getMClassRegisterMask(SpecialReg, "", true, Subtarget);
if (SYSmValue == -1)
return nullptr;
@@ -3755,10 +3730,10 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegi
return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
}
- std::pair<StringRef, StringRef> Fields;
- Fields = StringRef(SpecialReg).rsplit('_');
- std::string Reg = Fields.first.str();
- StringRef Flags = Fields.second;
+ SmallVector<StringRef, 5> Fields;
+ StringRef(SpecialReg).split(Fields, '_', 1, false);
+ std::string Reg = Fields[0].str();
+ StringRef Flags = Fields.size() == 2 ? Fields[1] : "";
// If the target was M Class then need to validate the special register value
// and retrieve the mask for use in the instruction node.
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jan 15 12:31:29 2016
@@ -272,12 +272,6 @@ class ARMAsmParser : public MCTargetAsmP
bool hasV8MBaseline() const {
return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
}
- bool hasV8MMainline() const {
- return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
- }
- bool has8MSecExt() const {
- return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
- }
bool hasARM() const {
return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
}
@@ -3978,18 +3972,6 @@ ARMAsmParser::parseMSRMaskOperand(Operan
.Case("basepri_max", 0x812)
.Case("faultmask", 0x813)
.Case("control", 0x814)
- .Case("msplim", 0x80a)
- .Case("psplim", 0x80b)
- .Case("msp_ns", 0x888)
- .Case("psp_ns", 0x889)
- .Case("msplim_ns", 0x88a)
- .Case("psplim_ns", 0x88b)
- .Case("primask_ns", 0x890)
- .Case("basepri_ns", 0x891)
- .Case("basepri_max_ns", 0x892)
- .Case("faultmask_ns", 0x893)
- .Case("control_ns", 0x894)
- .Case("sp_ns", 0x898)
.Default(~0U);
if (FlagsVal == ~0U)
@@ -4004,14 +3986,6 @@ ARMAsmParser::parseMSRMaskOperand(Operan
// basepri, basepri_max and faultmask only valid for V7m.
return MatchOperand_NoMatch;
- if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||
- (FlagsVal > 0x814 && FlagsVal < 0xc00)))
- return MatchOperand_NoMatch;
-
- if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||
- (FlagsVal > 0x890 && FlagsVal <= 0x893)))
- return MatchOperand_NoMatch;
-
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
return MatchOperand_Success;
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Jan 15 12:31:29 2016
@@ -4096,24 +4096,6 @@ static DecodeStatus DecodeMSRMask(MCInst
// Values basepri, basepri_max and faultmask are only valid for v7m.
return MCDisassembler::Fail;
break;
- case 0x8a: // msplim_ns
- case 0x8b: // psplim_ns
- case 0x91: // basepri_ns
- case 0x92: // basepri_max_ns
- case 0x93: // faultmask_ns
- if (!(FeatureBits[ARM::HasV8MMainlineOps]))
- return MCDisassembler::Fail;
- // fall through
- case 10: // msplim
- case 11: // psplim
- case 0x88: // msp_ns
- case 0x89: // psp_ns
- case 0x90: // primask_ns
- case 0x94: // control_ns
- case 0x98: // sp_ns
- if (!(FeatureBits[ARM::Feature8MSecExt]))
- return MCDisassembler::Fail;
- break;
default:
return MCDisassembler::Fail;
}
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Fri Jan 15 12:31:29 2016
@@ -901,42 +901,6 @@ void ARMInstPrinter::printMSRMaskOperand
case 20:
O << "control";
return;
- case 10:
- O << "msplim";
- return;
- case 11:
- O << "psplim";
- return;
- case 0x88:
- O << "msp_ns";
- return;
- case 0x89:
- O << "psp_ns";
- return;
- case 0x8a:
- O << "msplim_ns";
- return;
- case 0x8b:
- O << "psplim_ns";
- return;
- case 0x90:
- O << "primask_ns";
- return;
- case 0x91:
- O << "basepri_ns";
- return;
- case 0x92:
- O << "basepri_max_ns";
- return;
- case 0x93:
- O << "faultmask_ns";
- return;
- case 0x94:
- O << "control_ns";
- return;
- case 0x98:
- O << "sp_ns";
- return;
}
}
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s (original)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s Fri Jan 15 12:31:29 2016
@@ -54,9 +54,6 @@
// Tag_DIV_use (=44)
.eabi_attribute 44, 2
-// Tag_DSP_extension (=46)
-.eabi_attribute 46, 1
-
// Tag_Virtualization_use (=68)
.eabi_attribute 68, 3
@@ -74,15 +71,15 @@
// CHECK-NEXT: ]
// CHECK-NEXT: Address: 0x0
// CHECK-NEXT: Offset: 0x34
-// CHECK-NEXT: Size: 73
+// CHECK-NEXT: Size: 71
// CHECK-NEXT: Link: 0
// CHECK-NEXT: Info: 0
// CHECK-NEXT: AddressAlignment: 1
// CHECK-NEXT: EntrySize: 0
// CHECK-NEXT: SectionData (
-// CHECK-NEXT: 0000: 41480000 00616561 62690001 3E000000
+// CHECK-NEXT: 0000: 41460000 00616561 62690001 3C000000
// CHECK-NEXT: 0010: 05636F72 7465782D 61380006 0A074108
// CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119
-// CHECK-NEXT: 0030: 011B001C 0124012A 012C022E 0144036E
-// CHECK-NEXT: 0040: A0018101 3100FA01 01
+// CHECK-NEXT: 0030: 011B001C 0124012A 012C0244 036EA001
+// CHECK-NEXT: 0040: 81013100 FA0101
// CHECK-NEXT: )
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Fri Jan 15 12:31:29 2016
@@ -29,7 +29,6 @@
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
; RUN: llc < %s -mtriple=thumbv8m.base-linux-gnueabi | FileCheck %s --check-prefix=V8MBASELINE
; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi | FileCheck %s --check-prefix=V8MMAINLINE
-; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi -mattr=+dsp | FileCheck %s --check-prefix=V8MMAINLINE_DSP
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
@@ -392,14 +391,6 @@
; V8MMAINLINE: .eabi_attribute 7, 77
; V8MMAINLINE: .eabi_attribute 8, 0
; V8MMAINLINE: .eabi_attribute 9, 3
-; V8MMAINLINE_DSP-NOT: .eabi_attribute 46
-
-; V8MMAINLINE_DSP: .syntax unified
-; V8MBASELINE_DSP: .eabi_attribute 6, 17
-; V8MBASELINE_DSP: .eabi_attribute 7, 77
-; V8MMAINLINE_DSP: .eabi_attribute 8, 0
-; V8MMAINLINE_DSP: .eabi_attribute 9, 3
-; V8MMAINLINE_DSP: .eabi_attribute 46, 1
; Tag_CPU_unaligned_access
; NO-STRICT-ALIGN: .eabi_attribute 34, 1
@@ -490,9 +481,6 @@
; CORTEX-A7-NOFPU: .eabi_attribute 44, 2
; CORTEX-A7-FPUV4: .eabi_attribute 44, 2
-; Tag_DSP_extension
-; CORTEX-A7-CHECK-NOT: .eabi_attribute 46
-
; Tag_Virtualization_use
; CORTEX-A7-CHECK: .eabi_attribute 68, 3
; CORTEX-A7-NOFPU: .eabi_attribute 68, 3
Removed: llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll?rev=257915&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/special-reg-v8m-base.ll (removed)
@@ -1,142 +0,0 @@
-; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M
-; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s
-
-; V7M: LLVM ERROR: Invalid register name "sp_ns".
-
-define i32 @read_mclass_registers() nounwind {
-entry:
- ; CHECK-LABEL: read_mclass_registers:
- ; CHECK: mrs r0, apsr
- ; CHECK: mrs r1, iapsr
- ; CHECK: mrs r1, eapsr
- ; CHECK: mrs r1, xpsr
- ; CHECK: mrs r1, ipsr
- ; CHECK: mrs r1, epsr
- ; CHECK: mrs r1, iepsr
- ; CHECK: mrs r1, msp
- ; CHECK: mrs r1, psp
- ; CHECK: mrs r1, primask
- ; CHECK: mrs r1, control
- ; CHECK: mrs r1, msplim
- ; CHECK: mrs r1, psplim
- ; CHECK: mrs r1, msp_ns
- ; CHECK: mrs r1, psp_ns
- ; CHECK: mrs r1, primask_ns
- ; CHECK: mrs r1, control_ns
- ; CHECK: mrs r1, sp_ns
-
- %0 = call i32 @llvm.read_register.i32(metadata !0)
- %1 = call i32 @llvm.read_register.i32(metadata !4)
- %add1 = add i32 %1, %0
- %2 = call i32 @llvm.read_register.i32(metadata !8)
- %add2 = add i32 %add1, %2
- %3 = call i32 @llvm.read_register.i32(metadata !12)
- %add3 = add i32 %add2, %3
- %4 = call i32 @llvm.read_register.i32(metadata !16)
- %add4 = add i32 %add3, %4
- %5 = call i32 @llvm.read_register.i32(metadata !17)
- %add5 = add i32 %add4, %5
- %6 = call i32 @llvm.read_register.i32(metadata !18)
- %add6 = add i32 %add5, %6
- %7 = call i32 @llvm.read_register.i32(metadata !19)
- %add7 = add i32 %add6, %7
- %8 = call i32 @llvm.read_register.i32(metadata !20)
- %add8 = add i32 %add7, %8
- %9 = call i32 @llvm.read_register.i32(metadata !21)
- %add9 = add i32 %add8, %9
- %10 = call i32 @llvm.read_register.i32(metadata !25)
- %add10 = add i32 %add9, %10
- %11 = call i32 @llvm.read_register.i32(metadata !26)
- %add11 = add i32 %add10, %11
- %12 = call i32 @llvm.read_register.i32(metadata !27)
- %add12 = add i32 %add11, %12
- %13 = call i32 @llvm.read_register.i32(metadata !28)
- %add13 = add i32 %add12, %13
- %14 = call i32 @llvm.read_register.i32(metadata !29)
- %add14 = add i32 %add13, %14
- %15 = call i32 @llvm.read_register.i32(metadata !32)
- %add15 = add i32 %add14, %15
- %16 = call i32 @llvm.read_register.i32(metadata !35)
- %add16 = add i32 %add15, %16
- %17 = call i32 @llvm.read_register.i32(metadata !36)
- %add17 = add i32 %add16, %17
- ret i32 %add10
-}
-
-define void @write_mclass_registers(i32 %x) nounwind {
-entry:
- ; CHECK-LABEL: write_mclass_registers:
- ; CHECK: msr apsr, r0
- ; CHECK: msr apsr, r0
- ; CHECK: msr iapsr, r0
- ; CHECK: msr iapsr, r0
- ; CHECK: msr eapsr, r0
- ; CHECK: msr eapsr, r0
- ; CHECK: msr xpsr, r0
- ; CHECK: msr xpsr, r0
- ; CHECK: msr ipsr, r0
- ; CHECK: msr epsr, r0
- ; CHECK: msr iepsr, r0
- ; CHECK: msr msp, r0
- ; CHECK: msr psp, r0
- ; CHECK: msr primask, r0
- ; CHECK: msr control, r0
- ; CHECK: msr msplim, r0
- ; CHECK: msr psplim, r0
- ; CHECK: msr msp_ns, r0
- ; CHECK: msr psp_ns, r0
- ; CHECK: msr primask_ns, r0
- ; CHECK: msr control_ns, r0
- ; CHECK: msr sp_ns, r0
-
- call void @llvm.write_register.i32(metadata !0, i32 %x)
- call void @llvm.write_register.i32(metadata !1, i32 %x)
- call void @llvm.write_register.i32(metadata !4, i32 %x)
- call void @llvm.write_register.i32(metadata !5, i32 %x)
- call void @llvm.write_register.i32(metadata !8, i32 %x)
- call void @llvm.write_register.i32(metadata !9, i32 %x)
- call void @llvm.write_register.i32(metadata !12, i32 %x)
- call void @llvm.write_register.i32(metadata !13, i32 %x)
- call void @llvm.write_register.i32(metadata !16, i32 %x)
- call void @llvm.write_register.i32(metadata !17, i32 %x)
- call void @llvm.write_register.i32(metadata !18, i32 %x)
- call void @llvm.write_register.i32(metadata !19, i32 %x)
- call void @llvm.write_register.i32(metadata !20, i32 %x)
- call void @llvm.write_register.i32(metadata !21, i32 %x)
- call void @llvm.write_register.i32(metadata !25, i32 %x)
- call void @llvm.write_register.i32(metadata !26, i32 %x)
- call void @llvm.write_register.i32(metadata !27, i32 %x)
- call void @llvm.write_register.i32(metadata !28, i32 %x)
- call void @llvm.write_register.i32(metadata !29, i32 %x)
- call void @llvm.write_register.i32(metadata !32, i32 %x)
- call void @llvm.write_register.i32(metadata !35, i32 %x)
- call void @llvm.write_register.i32(metadata !36, i32 %x)
- ret void
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-declare void @llvm.write_register.i32(metadata, i32) nounwind
-
-!0 = !{!"apsr"}
-!1 = !{!"apsr_nzcvq"}
-!4 = !{!"iapsr"}
-!5 = !{!"iapsr_nzcvq"}
-!8 = !{!"eapsr"}
-!9 = !{!"eapsr_nzcvq"}
-!12 = !{!"xpsr"}
-!13 = !{!"xpsr_nzcvq"}
-!16 = !{!"ipsr"}
-!17 = !{!"epsr"}
-!18 = !{!"iepsr"}
-!19 = !{!"msp"}
-!20 = !{!"psp"}
-!21 = !{!"primask"}
-!25 = !{!"control"}
-!26 = !{!"msplim"}
-!27 = !{!"psplim"}
-!28 = !{!"msp_ns"}
-!29 = !{!"psp_ns"}
-!32 = !{!"primask_ns"}
-!35 = !{!"control_ns"}
-!36 = !{!"sp_ns"}
-
Removed: llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll?rev=257915&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/special-reg-v8m-main.ll (removed)
@@ -1,214 +0,0 @@
-; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE
-; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE
-
-; BASELINE: LLVM ERROR: Invalid register name "basepri_max_ns".
-
-define i32 @read_mclass_registers() nounwind {
-entry:
- ; MAINLINE-LABEL: read_mclass_registers:
- ; MAINLINE: mrs r0, apsr
- ; MAINLINE: mrs r1, iapsr
- ; MAINLINE: mrs r1, eapsr
- ; MAINLINE: mrs r1, xpsr
- ; MAINLINE: mrs r1, ipsr
- ; MAINLINE: mrs r1, epsr
- ; MAINLINE: mrs r1, iepsr
- ; MAINLINE: mrs r1, msp
- ; MAINLINE: mrs r1, psp
- ; MAINLINE: mrs r1, primask
- ; MAINLINE: mrs r1, basepri
- ; MAINLINE: mrs r1, basepri_max
- ; MAINLINE: mrs r1, faultmask
- ; MAINLINE: mrs r1, control
- ; MAINLINE: mrs r1, msplim
- ; MAINLINE: mrs r1, psplim
- ; MAINLINE: mrs r1, msp_ns
- ; MAINLINE: mrs r1, psp_ns
- ; MAINLINE: mrs r1, msplim_ns
- ; MAINLINE: mrs r1, psplim_ns
- ; MAINLINE: mrs r1, primask_ns
- ; MAINLINE: mrs r1, basepri_ns
- ; MAINLINE: mrs r1, faultmask_ns
- ; MAINLINE: mrs r1, control_ns
- ; MAINLINE: mrs r1, sp_ns
- ; MAINLINE: mrs r1, basepri_max_ns
-
- %0 = call i32 @llvm.read_register.i32(metadata !0)
- %1 = call i32 @llvm.read_register.i32(metadata !4)
- %add1 = add i32 %1, %0
- %2 = call i32 @llvm.read_register.i32(metadata !8)
- %add2 = add i32 %add1, %2
- %3 = call i32 @llvm.read_register.i32(metadata !12)
- %add3 = add i32 %add2, %3
- %4 = call i32 @llvm.read_register.i32(metadata !16)
- %add4 = add i32 %add3, %4
- %5 = call i32 @llvm.read_register.i32(metadata !17)
- %add5 = add i32 %add4, %5
- %6 = call i32 @llvm.read_register.i32(metadata !18)
- %add6 = add i32 %add5, %6
- %7 = call i32 @llvm.read_register.i32(metadata !19)
- %add7 = add i32 %add6, %7
- %8 = call i32 @llvm.read_register.i32(metadata !20)
- %add8 = add i32 %add7, %8
- %9 = call i32 @llvm.read_register.i32(metadata !21)
- %add9 = add i32 %add8, %9
- %10 = call i32 @llvm.read_register.i32(metadata !22)
- %add10 = add i32 %add9, %10
- %11 = call i32 @llvm.read_register.i32(metadata !23)
- %add11 = add i32 %add10, %11
- %12 = call i32 @llvm.read_register.i32(metadata !24)
- %add12 = add i32 %add11, %12
- %13 = call i32 @llvm.read_register.i32(metadata !25)
- %add13 = add i32 %add12, %13
- %14 = call i32 @llvm.read_register.i32(metadata !26)
- %add14 = add i32 %add13, %14
- %15 = call i32 @llvm.read_register.i32(metadata !27)
- %add15 = add i32 %add14, %15
- %16 = call i32 @llvm.read_register.i32(metadata !28)
- %add16 = add i32 %add15, %16
- %17 = call i32 @llvm.read_register.i32(metadata !29)
- %add17 = add i32 %add16, %17
- %18 = call i32 @llvm.read_register.i32(metadata !30)
- %add18 = add i32 %add17, %18
- %19 = call i32 @llvm.read_register.i32(metadata !31)
- %add19 = add i32 %add18, %19
- %20 = call i32 @llvm.read_register.i32(metadata !32)
- %add20 = add i32 %add19, %20
- %21 = call i32 @llvm.read_register.i32(metadata !33)
- %add21 = add i32 %add20, %21
- %22 = call i32 @llvm.read_register.i32(metadata !34)
- %add22 = add i32 %add21, %22
- %23 = call i32 @llvm.read_register.i32(metadata !35)
- %add23 = add i32 %add22, %23
- %24 = call i32 @llvm.read_register.i32(metadata !36)
- %add24 = add i32 %add23, %24
- %25 = call i32 @llvm.read_register.i32(metadata !37)
- %add25 = add i32 %add24, %25
- ret i32 %add25
-}
-
-define void @write_mclass_registers(i32 %x) nounwind {
-entry:
- ; MAINLINE-LABEL: write_mclass_registers:
- ; MAINLINE: msr apsr_nzcvqg, r0
- ; MAINLINE: msr apsr_nzcvq, r0
- ; MAINLINE: msr apsr_g, r0
- ; MAINLINE: msr apsr_nzcvqg, r0
- ; MAINLINE: msr iapsr_nzcvqg, r0
- ; MAINLINE: msr iapsr_nzcvq, r0
- ; MAINLINE: msr iapsr_g, r0
- ; MAINLINE: msr iapsr_nzcvqg, r0
- ; MAINLINE: msr eapsr_nzcvqg, r0
- ; MAINLINE: msr eapsr_nzcvq, r0
- ; MAINLINE: msr eapsr_g, r0
- ; MAINLINE: msr eapsr_nzcvqg, r0
- ; MAINLINE: msr xpsr_nzcvqg, r0
- ; MAINLINE: msr xpsr_nzcvq, r0
- ; MAINLINE: msr xpsr_g, r0
- ; MAINLINE: msr xpsr_nzcvqg, r0
- ; MAINLINE: msr ipsr, r0
- ; MAINLINE: msr epsr, r0
- ; MAINLINE: msr iepsr, r0
- ; MAINLINE: msr msp, r0
- ; MAINLINE: msr psp, r0
- ; MAINLINE: msr primask, r0
- ; MAINLINE: msr basepri, r0
- ; MAINLINE: msr basepri_max, r0
- ; MAINLINE: msr faultmask, r0
- ; MAINLINE: msr control, r0
- ; MAINLINE: msr msplim, r0
- ; MAINLINE: msr psplim, r0
- ; MAINLINE: msr msp_ns, r0
- ; MAINLINE: msr psp_ns, r0
- ; MAINLINE: msr msplim_ns, r0
- ; MAINLINE: msr psplim_ns, r0
- ; MAINLINE: msr primask_ns, r0
- ; MAINLINE: msr basepri_ns, r0
- ; MAINLINE: msr faultmask_ns, r0
- ; MAINLINE: msr control_ns, r0
- ; MAINLINE: msr sp_ns, r0
- ; MAINLINE: msr basepri_max_ns, r0
-
- call void @llvm.write_register.i32(metadata !0, i32 %x)
- call void @llvm.write_register.i32(metadata !1, i32 %x)
- call void @llvm.write_register.i32(metadata !2, i32 %x)
- call void @llvm.write_register.i32(metadata !3, i32 %x)
- call void @llvm.write_register.i32(metadata !4, i32 %x)
- call void @llvm.write_register.i32(metadata !5, i32 %x)
- call void @llvm.write_register.i32(metadata !6, i32 %x)
- call void @llvm.write_register.i32(metadata !7, i32 %x)
- call void @llvm.write_register.i32(metadata !8, i32 %x)
- call void @llvm.write_register.i32(metadata !9, i32 %x)
- call void @llvm.write_register.i32(metadata !10, i32 %x)
- call void @llvm.write_register.i32(metadata !11, i32 %x)
- call void @llvm.write_register.i32(metadata !12, i32 %x)
- call void @llvm.write_register.i32(metadata !13, i32 %x)
- call void @llvm.write_register.i32(metadata !14, i32 %x)
- call void @llvm.write_register.i32(metadata !15, i32 %x)
- call void @llvm.write_register.i32(metadata !16, i32 %x)
- call void @llvm.write_register.i32(metadata !17, i32 %x)
- call void @llvm.write_register.i32(metadata !18, i32 %x)
- call void @llvm.write_register.i32(metadata !19, i32 %x)
- call void @llvm.write_register.i32(metadata !20, i32 %x)
- call void @llvm.write_register.i32(metadata !21, i32 %x)
- call void @llvm.write_register.i32(metadata !22, i32 %x)
- call void @llvm.write_register.i32(metadata !23, i32 %x)
- call void @llvm.write_register.i32(metadata !24, i32 %x)
- call void @llvm.write_register.i32(metadata !25, i32 %x)
- call void @llvm.write_register.i32(metadata !26, i32 %x)
- call void @llvm.write_register.i32(metadata !27, i32 %x)
- call void @llvm.write_register.i32(metadata !28, i32 %x)
- call void @llvm.write_register.i32(metadata !29, i32 %x)
- call void @llvm.write_register.i32(metadata !30, i32 %x)
- call void @llvm.write_register.i32(metadata !31, i32 %x)
- call void @llvm.write_register.i32(metadata !32, i32 %x)
- call void @llvm.write_register.i32(metadata !33, i32 %x)
- call void @llvm.write_register.i32(metadata !34, i32 %x)
- call void @llvm.write_register.i32(metadata !35, i32 %x)
- call void @llvm.write_register.i32(metadata !36, i32 %x)
- call void @llvm.write_register.i32(metadata !37, i32 %x)
- ret void
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-declare void @llvm.write_register.i32(metadata, i32) nounwind
-
-!0 = !{!"apsr"}
-!1 = !{!"apsr_nzcvq"}
-!2 = !{!"apsr_g"}
-!3 = !{!"apsr_nzcvqg"}
-!4 = !{!"iapsr"}
-!5 = !{!"iapsr_nzcvq"}
-!6 = !{!"iapsr_g"}
-!7 = !{!"iapsr_nzcvqg"}
-!8 = !{!"eapsr"}
-!9 = !{!"eapsr_nzcvq"}
-!10 = !{!"eapsr_g"}
-!11 = !{!"eapsr_nzcvqg"}
-!12 = !{!"xpsr"}
-!13 = !{!"xpsr_nzcvq"}
-!14 = !{!"xpsr_g"}
-!15 = !{!"xpsr_nzcvqg"}
-!16 = !{!"ipsr"}
-!17 = !{!"epsr"}
-!18 = !{!"iepsr"}
-!19 = !{!"msp"}
-!20 = !{!"psp"}
-!21 = !{!"primask"}
-!22 = !{!"basepri"}
-!23 = !{!"basepri_max"}
-!24 = !{!"faultmask"}
-!25 = !{!"control"}
-!26 = !{!"msplim"}
-!27 = !{!"psplim"}
-!28 = !{!"msp_ns"}
-!29 = !{!"psp_ns"}
-!30 = !{!"msplim_ns"}
-!31 = !{!"psplim_ns"}
-!32 = !{!"primask_ns"}
-!33 = !{!"basepri_ns"}
-!34 = !{!"faultmask_ns"}
-!35 = !{!"control_ns"}
-!36 = !{!"sp_ns"}
-!37 = !{!"basepri_max_ns"}
-
Modified: llvm/trunk/test/MC/ARM/directive-eabi_attribute.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-eabi_attribute.s?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-eabi_attribute.s (original)
+++ llvm/trunk/test/MC/ARM/directive-eabi_attribute.s Fri Jan 15 12:31:29 2016
@@ -209,12 +209,6 @@
@ CHECK-OBJ-NEXT: Value: 0
@ CHECK-OBJ-NEXT: TagName: DIV_use
@ CHECK-OBJ-NEXT: Description: If Available
- .eabi_attribute Tag_DSP_extension, 0
-@ CHECK: .eabi_attribute 46, 0
-@ CHECK-OBJ: Tag: 46
-@ CHECK-OBJ-NEXT: Value: 0
-@ CHECK-OBJ-NEXT: TagName: DSP_extension
-@ CHECK-OBJ-NEXT: Description: Not Permitted
.eabi_attribute Tag_nodefaults, 0
@ CHECK: .eabi_attribute 64, 0
@ CHECK-OBJ: Tag: 64
Modified: llvm/trunk/test/MC/ARM/thumbv8m.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8m.s?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumbv8m.s (original)
+++ llvm/trunk/test/MC/ARM/thumbv8m.s Fri Jan 15 12:31:29 2016
@@ -4,30 +4,16 @@
// RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-MAINLINE --check-prefix=CHECK %s
// RUN: FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s
-// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+dsp,+t2xtpk -show-encoding < %s 2>%t \
-// RUN: | FileCheck --check-prefix=CHECK-MAINLINE_DSP --check-prefix=CHECK %s
-// RUN: FileCheck --check-prefix=UNDEF-MAINLINE_DSP --check-prefix=UNDEF < %t %s
// Simple check that baseline is v6M and mainline is v7M
// UNDEF-BASELINE: error: instruction requires: thumb2
// UNDEF-MAINLINE-NOT: error: instruction requires:
-// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
mov.w r0, r0
// Check that .arm is invalid
// UNDEF: target does not support ARM mode
.arm
-// And only +dsp,+t2xtpk has DSP and t2xtpk instructions
-// UNDEF-BASELINE: error: instruction requires: arm-mode
-// UNDEF-MAINLINE: error: instruction requires: arm-mode
-// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
-qadd16 r0, r0, r0
-// UNDEF-BASELINE: error: instruction requires: arm-mode
-// UNDEF-MAINLINE: error: instruction requires: arm-mode
-// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
-uxtab16 r0, r1, r2
-
// Instruction availibility checks
// 'Barrier instructions'
@@ -171,50 +157,12 @@ ttat r0, r1
// UNDEF-BASELINE: error: instruction requires: armv8m.main
// CHECK-MAINLINE: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]
-// CHECK-MAINLINE_DSP: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]
vlldm r5
// UNDEF-BASELINE: error: instruction requires: armv8m.main
// CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
-// CHECK-MAINLINE_DSP: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
vlstm r10
-// New SYSm's
-
-MRS r1, MSP_NS
-// CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]
-MSR PSP_NS, r2
-// CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]
-MRS r3, PRIMASK_NS
-// CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]
-MSR CONTROL_NS, r4
-// CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]
-MRS r5, SP_NS
-// CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]
-MRS r6,MSPLIM
-// CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]
-MRS r7,PSPLIM
-// CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]
-MSR MSPLIM,r8
-// CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]
-MSR PSPLIM,r9
-// CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]
-
-MRS r10, MSPLIM_NS
-// CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
-// UNDEF-BASELINE: error: invalid operand for instruction
-MSR PSPLIM_NS, r11
-// CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
-// UNDEF-BASELINE: error: invalid operand for instruction
-MRS r12, BASEPRI_NS
-// CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]
-// UNDEF-BASELINE: error: invalid operand for instruction
-MRS r12, BASEPRI_MAX_NS
-// CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c]
-// UNDEF-BASELINE: error: invalid operand for instruction
-MSR FAULTMASK_NS, r14
-// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
-// UNDEF-BASELINE: error: invalid operand for instruction
// Invalid operand tests
// UNDEF: error: invalid operand for instruction
Removed: llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt?rev=257915&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8m.txt (removed)
@@ -1,25 +0,0 @@
-# RUN: llvm-mc -triple=thumbv8m.base -disassemble < %s 2>%t | FileCheck %s
-# RUN: FileCheck < %t %s --check-prefix=CHECK-STDERR
-# RUN: llvm-mc -triple=thumbv8m.main -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAINLINE
-
-0xef 0xf3 0x0a 0x83
-# CHECK: mrs r3, msplim
-0xef 0xf3 0x0b 0x84
-# CHECK: mrs r4, psplim
-0x8b 0xf3 0x0a 0x88
-# CHECK: msr msplim, r11
-0x8c 0xf3 0x0b 0x88
-# CHECK: msr psplim, r12
-
-0xef 0xf3 0x90 0x86
-# CHECK: mrs r6, primask_ns
-0x88 0xf3 0x98 0x88
-# CHECK: msr sp_ns, r8
-
-0xef 0xf3 0x8a 0x85
-# CHECK-STDERR: warning: invalid instruction encoding
-# CHECK-MAINLINE: mrs r5, msplim_ns
-0x87 0xf3 0x93 0x88
-# CHECK-STDERR: warning: invalid instruction encoding
-# CHECK-MAINLINE: msr faultmask_ns, r7
-
Modified: llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s (original)
+++ llvm/trunk/test/tools/llvm-readobj/ARM/attribute-0.s Fri Jan 15 12:31:29 2016
@@ -225,13 +225,6 @@
@CHECK-OBJ-NEXT: TagName: DIV_use
@CHECK-OBJ-NEXT: Description: If Available
-.eabi_attribute Tag_DSP_extension, 0
- at CHECK: .eabi_attribute 46, 0
- at CHECK-OBJ: Tag: 46
- at CHECK-OBJ-NEXT: Value: 0
- at CHECK-OBJ-NEXT: TagName: DSP_extension
- at CHECK-OBJ-NEXT: Description: Not Permitted
-
.eabi_attribute Tag_Virtualization_use, 0
@CHECK: .eabi_attribute 68, 0
@CHECK-OBJ: Tag: 68
Modified: llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s (original)
+++ llvm/trunk/test/tools/llvm-readobj/ARM/attribute-1.s Fri Jan 15 12:31:29 2016
@@ -211,13 +211,6 @@
@CHECK-OBJ-NEXT: TagName: DIV_use
@CHECK-OBJ-NEXT: Description: Not Permitted
-.eabi_attribute Tag_DSP_extension, 1
- at CHECK: .eabi_attribute 46, 1
- at CHECK-OBJ: Tag: 46
- at CHECK-OBJ-NEXT: Value: 1
- at CHECK-OBJ-NEXT: TagName: DSP_extension
- at CHECK-OBJ-NEXT: Description: Permitted
-
.eabi_attribute Tag_Virtualization_use, 1
@CHECK: .eabi_attribute 68, 1
@CHECK-OBJ: Tag: 68
Modified: llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp (original)
+++ llvm/trunk/tools/llvm-readobj/ARMAttributeParser.cpp Fri Jan 15 12:31:29 2016
@@ -63,7 +63,6 @@ ARMAttributeParser::DisplayRoutines[] =
ATTRIBUTE_HANDLER(ABI_FP_16bit_format),
ATTRIBUTE_HANDLER(MPextension_use),
ATTRIBUTE_HANDLER(DIV_use),
- ATTRIBUTE_HANDLER(DSP_extension),
ATTRIBUTE_HANDLER(T2EE_use),
ATTRIBUTE_HANDLER(Virtualization_use),
ATTRIBUTE_HANDLER(nodefaults)
@@ -514,16 +513,6 @@ void ARMAttributeParser::DIV_use(AttrTyp
uint64_t Value = ParseInteger(Data, Offset);
StringRef ValueDesc =
- (Value < array_lengthof(Strings)) ? Strings[Value] : nullptr;
- PrintAttribute(Tag, Value, ValueDesc);
-}
-
-void ARMAttributeParser::DSP_extension(AttrType Tag, const uint8_t *Data,
- uint32_t &Offset) {
- static const char *const Strings[] = { "Not Permitted", "Permitted" };
-
- uint64_t Value = ParseInteger(Data, Offset);
- StringRef ValueDesc =
(Value < array_lengthof(Strings)) ? Strings[Value] : nullptr;
PrintAttribute(Tag, Value, ValueDesc);
}
Modified: llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h?rev=257916&r1=257915&r2=257916&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h (original)
+++ llvm/trunk/tools/llvm-readobj/ARMAttributeParser.h Fri Jan 15 12:31:29 2016
@@ -100,8 +100,6 @@ class ARMAttributeParser {
uint32_t &Offset);
void DIV_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,
uint32_t &Offset);
- void DSP_extension(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,
- uint32_t &Offset);
void T2EE_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,
uint32_t &Offset);
void Virtualization_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data,
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