[PATCH] D16220: [mips] Fix RetCC_MipsN to promote types smaller than i64 to GPR-width.

[Vasileios Kalintiris via llvm-commits]

vkalintiris created this revision.
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.
vkalintiris added a dependency: D10970: [mips] Promote the result of SETCC nodes to GPR width..
Herald added a subscriber: dsanders.

In order to avoid a number of redundant sign/zero-extensions, we have
to custom combine AssertSext on our target and fold a generic pattern
in the target independent DAG combiner for the SIGN_EXTEND_INREG node.

Depends on D10970

http://reviews.llvm.org/D16220

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/Mips/MipsCallingConv.td
  lib/Target/Mips/MipsISelLowering.cpp
  test/CodeGen/Mips/atomic.ll
  test/CodeGen/Mips/cconv/return.ll
  test/CodeGen/Mips/delay-slot-kill.ll
  test/CodeGen/Mips/fcmp.ll
  test/CodeGen/Mips/llvm-ir/add.ll
  test/CodeGen/Mips/llvm-ir/and.ll
  test/CodeGen/Mips/llvm-ir/ashr.ll
  test/CodeGen/Mips/llvm-ir/lshr.ll
  test/CodeGen/Mips/llvm-ir/mul.ll
  test/CodeGen/Mips/llvm-ir/or.ll
  test/CodeGen/Mips/llvm-ir/ret.ll
  test/CodeGen/Mips/llvm-ir/sdiv.ll
  test/CodeGen/Mips/llvm-ir/select-flt.ll
  test/CodeGen/Mips/llvm-ir/select-int.ll
  test/CodeGen/Mips/llvm-ir/select.ll
  test/CodeGen/Mips/llvm-ir/shl.ll
  test/CodeGen/Mips/llvm-ir/srem.ll
  test/CodeGen/Mips/llvm-ir/sub.ll
  test/CodeGen/Mips/llvm-ir/udiv.ll
  test/CodeGen/Mips/llvm-ir/urem.ll
  test/CodeGen/Mips/llvm-ir/xor.ll
  test/CodeGen/Mips/msa/basic_operations.ll
  test/CodeGen/Mips/named-register-n32.ll

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