[llvm] r257811 - [Hexagon] Handle HVX registers in bit simplification

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Jan 14 15:45:43 2016
New Revision: 257811

URL: http://llvm.org/viewvc/llvm-project?rev=257811&view=rev
Log:
[Hexagon] Handle HVX registers in bit simplification

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=257811&r1=257810&r2=257811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Thu Jan 14 15:45:43 2016
@@ -876,6 +876,12 @@ const TargetRegisterClass *HexagonBitSim
     case Hexagon::DoubleRegsRegClassID:
       VerifySR(RR.Sub);
       return &Hexagon::IntRegsRegClass;
+    case Hexagon::VecDblRegsRegClassID:
+      VerifySR(RR.Sub);
+      return &Hexagon::VectorRegsRegClass;
+    case Hexagon::VecDblRegs128BRegClassID:
+      VerifySR(RR.Sub);
+      return &Hexagon::VectorRegs128BRegClass;
   }
   return nullptr;
 }