[llvm] r257805 - [Packetizer] Code cleanup, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 14 13:17:05 PST 2016
Author: kparzysz
Date: Thu Jan 14 15:17:04 2016
New Revision: 257805
URL: http://llvm.org/viewvc/llvm-project?rev=257805&view=rev
Log:
[Packetizer] Code cleanup, NFC
Modified:
llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h
llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=257805&r1=257804&r2=257805&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h Thu Jan 14 15:17:04 2016
@@ -80,7 +80,7 @@ private:
// CachedTable is a map from <FromState, Input> to ToState.
DenseMap<UnsignPair, unsigned> CachedTable;
- // ReadTable - Read the DFA transition table and update CachedTable.
+ // Read the DFA transition table and update CachedTable.
void ReadTable(unsigned state);
public:
@@ -92,38 +92,39 @@ public:
CurrentState = 0;
}
- // getInsnInput - Return the DFAInput for an instruction class.
+ // Return the DFAInput for an instruction class.
DFAInput getInsnInput(unsigned InsnClass);
- // getInsnInput - Return the DFAInput for an instruction class input vector.
+ // Return the DFAInput for an instruction class input vector.
static DFAInput getInsnInput(const std::vector<unsigned> &InsnClass);
- // canReserveResources - Check if the resources occupied by a MCInstrDesc
- // are available in the current state.
+ // Check if the resources occupied by a MCInstrDesc are available in
+ // the current state.
bool canReserveResources(const llvm::MCInstrDesc *MID);
- // reserveResources - Reserve the resources occupied by a MCInstrDesc and
- // change the current state to reflect that change.
+ // Reserve the resources occupied by a MCInstrDesc and change the current
+ // state to reflect that change.
void reserveResources(const llvm::MCInstrDesc *MID);
- // canReserveResources - Check if the resources occupied by a machine
- // instruction are available in the current state.
+ // Check if the resources occupied by a machine instruction are available
+ // in the current state.
bool canReserveResources(llvm::MachineInstr *MI);
- // reserveResources - Reserve the resources occupied by a machine
- // instruction and change the current state to reflect that change.
+ // Reserve the resources occupied by a machine instruction and change the
+ // current state to reflect that change.
void reserveResources(llvm::MachineInstr *MI);
const InstrItineraryData *getInstrItins() const { return InstrItins; }
};
-// VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
-// packetizer works on machine basic blocks. For each instruction I in BB, the
-// packetizer consults the DFA to see if machine resources are available to
-// execute I. If so, the packetizer checks if I depends on any instruction J in
-// the current packet. If no dependency is found, I is added to current packet
-// and machine resource is marked as taken. If any dependency is found, a target
-// API call is made to prune the dependence.
+
+// VLIWPacketizerList implements a simple VLIW packetizer using DFA. The
+// packetizer works on machine basic blocks. For each instruction I in BB,
+// the packetizer consults the DFA to see if machine resources are available
+// to execute I. If so, the packetizer checks if I depends on any instruction
+// in the current packet. If no dependency is found, I is added to current
+// packet and the machine resource is marked as taken. If any dependency is
+// found, a target API call is made to prune the dependence.
class VLIWPacketizerList {
protected:
MachineFunction &MF;
@@ -132,13 +133,11 @@ protected:
// The VLIW Scheduler.
DefaultVLIWScheduler *VLIWScheduler;
-
// Vector of instructions assigned to the current packet.
std::vector<MachineInstr*> CurrentPacketMIs;
// DFA resource tracker.
DFAPacketizer *ResourceTracker;
-
- // Generate MI -> SU map.
+ // Map: MI -> SU.
std::map<MachineInstr*, SUnit*> MIToSUnit;
public:
@@ -148,12 +147,12 @@ public:
virtual ~VLIWPacketizerList();
- // PacketizeMIs - Implement this API in the backend to bundle instructions.
+ // Implement this API in the backend to bundle instructions.
void PacketizeMIs(MachineBasicBlock *MBB,
MachineBasicBlock::iterator BeginItr,
MachineBasicBlock::iterator EndItr);
- // getResourceTracker - return ResourceTracker
+ // Return the ResourceTracker.
DFAPacketizer *getResourceTracker() {return ResourceTracker;}
// addToPacket - Add MI to the current packet.
@@ -169,19 +168,18 @@ public:
// to perform custom finalization.
virtual void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
- // initPacketizerState - perform initialization before packetizing
- // an instruction. This function is supposed to be overrided by
- // the target dependent packetizer.
- virtual void initPacketizerState() { return; }
+ // Perform initialization before packetizing an instruction. This
+ // function is supposed to be overrided by the target dependent packetizer.
+ virtual void initPacketizerState() {}
- // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
+ // Check if the given instruction I should be ignored by the packetizer.
virtual bool ignorePseudoInstruction(const MachineInstr *I,
const MachineBasicBlock *MBB) {
return false;
}
- // isSoloInstruction - return true if instruction MI can not be packetized
- // with any other instruction, which means that MI itself is a packet.
+ // Return true if instruction MI can not be packetized with any other
+ // instruction, which means that MI itself is a packet.
virtual bool isSoloInstruction(const MachineInstr *MI) {
return true;
}
@@ -196,19 +194,17 @@ public:
return true;
}
- // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
- // together.
+ // Check if it is legal to packetize SUI and SUJ together.
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
return false;
}
- // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
- // and SUJ.
+ // Check if it is legal to prune dependece between SUI and SUJ.
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
return false;
}
-
};
-}
+
+} // namespace llvm
#endif
Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=257805&r1=257804&r2=257805&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Thu Jan 14 15:17:04 2016
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Target/TargetInstrInfo.h"
+
using namespace llvm;
// --------------------------------------------------------------------
@@ -44,8 +45,8 @@ namespace {
/// DFAPacketizerEmitter.cpp.
DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
DFAInput InsnInput = 0;
- assert ((InsnClass.size() <= DFA_MAX_RESTERMS) &&
- "Exceeded maximum number of DFA terms");
+ assert((InsnClass.size() <= DFA_MAX_RESTERMS) &&
+ "Exceeded maximum number of DFA terms");
for (auto U : InsnClass)
InsnInput = addDFAFuncUnits(InsnInput, U);
return InsnInput;
@@ -66,8 +67,7 @@ DFAPacketizer::DFAPacketizer(const Instr
}
-//
-// ReadTable - Read the DFA transition table and update CachedTable.
+// Read the DFA transition table and update CachedTable.
//
// Format of the transition tables:
// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
@@ -80,8 +80,7 @@ void DFAPacketizer::ReadTable(unsigned i
unsigned NextStateInTable = DFAStateEntryTable[state+1];
// Early exit in case CachedTable has already contains this
// state's transitions.
- if (CachedTable.count(UnsignPair(state,
- DFAStateInputTable[ThisState][0])))
+ if (CachedTable.count(UnsignPair(state, DFAStateInputTable[ThisState][0])))
return;
for (unsigned i = ThisState; i < NextStateInTable; i++)
@@ -89,38 +88,41 @@ void DFAPacketizer::ReadTable(unsigned i
DFAStateInputTable[i][1];
}
-//
-// getInsnInput - Return the DFAInput for an instruction class.
-//
+
+// Return the DFAInput for an instruction class.
DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
// Note: this logic must match that in DFAPacketizerDefs.h for input vectors.
DFAInput InsnInput = 0;
unsigned i = 0;
+ (void)i;
for (const InstrStage *IS = InstrItins->beginStage(InsnClass),
- *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) {
+ *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS) {
InsnInput = addDFAFuncUnits(InsnInput, IS->getUnits());
- assert ((i < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs");
+ assert((i++ < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs");
}
return InsnInput;
}
-// getInsnInput - Return the DFAInput for an instruction class input vector.
+
+// Return the DFAInput for an instruction class input vector.
DFAInput DFAPacketizer::getInsnInput(const std::vector<unsigned> &InsnClass) {
return getDFAInsnInput(InsnClass);
}
-// canReserveResources - Check if the resources occupied by a MCInstrDesc
-// are available in the current state.
+
+// Check if the resources occupied by a MCInstrDesc are available in the
+// current state.
bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
unsigned InsnClass = MID->getSchedClass();
DFAInput InsnInput = getInsnInput(InsnClass);
UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
ReadTable(CurrentState);
- return (CachedTable.count(StateTrans) != 0);
+ return CachedTable.count(StateTrans) != 0;
}
-// reserveResources - Reserve the resources occupied by a MCInstrDesc and
-// change the current state to reflect that change.
+
+// Reserve the resources occupied by a MCInstrDesc and change the current
+// state to reflect that change.
void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
unsigned InsnClass = MID->getSchedClass();
DFAInput InsnInput = getInsnInput(InsnClass);
@@ -131,34 +133,37 @@ void DFAPacketizer::reserveResources(con
}
-// canReserveResources - Check if the resources occupied by a machine
-// instruction are available in the current state.
+// Check if the resources occupied by a machine instruction are available
+// in the current state.
bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
const llvm::MCInstrDesc &MID = MI->getDesc();
return canReserveResources(&MID);
}
-// reserveResources - Reserve the resources occupied by a machine
-// instruction and change the current state to reflect that change.
+
+// Reserve the resources occupied by a machine instruction and change the
+// current state to reflect that change.
void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
const llvm::MCInstrDesc &MID = MI->getDesc();
reserveResources(&MID);
}
+
namespace llvm {
-// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
-// Schedule method to build the dependence graph.
+// This class extends ScheduleDAGInstrs and overrides the schedule method
+// to build the dependence graph.
class DefaultVLIWScheduler : public ScheduleDAGInstrs {
private:
AliasAnalysis *AA;
public:
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
AliasAnalysis *AA);
- // Schedule - Actual scheduling work.
+ // Actual scheduling work.
void schedule() override;
};
}
+
DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
MachineLoopInfo &MLI,
AliasAnalysis *AA)
@@ -166,33 +171,31 @@ DefaultVLIWScheduler::DefaultVLIWSchedul
CanHandleTerminators = true;
}
+
void DefaultVLIWScheduler::schedule() {
// Build the scheduling graph.
buildSchedGraph(AA);
}
-// VLIWPacketizerList Ctor
-VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
- MachineLoopInfo &MLI, AliasAnalysis *AA)
- : MF(MF), AA(AA) {
- TII = MF.getSubtarget().getInstrInfo();
+
+VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,
+ MachineLoopInfo &mli, AliasAnalysis *aa)
+ : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
- VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, AA);
+ VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA);
}
-// VLIWPacketizerList Dtor
+
VLIWPacketizerList::~VLIWPacketizerList() {
if (VLIWScheduler)
delete VLIWScheduler;
-
if (ResourceTracker)
delete ResourceTracker;
}
-// endPacket - End the current packet, bundle packet instructions and reset
-// DFA state.
-void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
- MachineInstr *MI) {
+
+// End the current packet, bundle packet instructions and reset DFA state.
+void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineInstr *MI) {
if (CurrentPacketMIs.size() > 1) {
MachineInstr *MIFirst = CurrentPacketMIs.front();
finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator());
@@ -201,7 +204,8 @@ void VLIWPacketizerList::endPacket(Machi
ResourceTracker->clearResources();
}
-// PacketizeMIs - Bundle machine instructions into packets.
+
+// Bundle machine instructions into packets.
void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
MachineBasicBlock::iterator BeginItr,
MachineBasicBlock::iterator EndItr) {
@@ -213,25 +217,22 @@ void VLIWPacketizerList::PacketizeMIs(Ma
// Generate MI -> SU map.
MIToSUnit.clear();
- for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
- SUnit *SU = &VLIWScheduler->SUnits[i];
- MIToSUnit[SU->getInstr()] = SU;
- }
+ for (SUnit &SU : VLIWScheduler->SUnits)
+ MIToSUnit[SU.getInstr()] = &SU;
// The main packetizer loop.
for (; BeginItr != EndItr; ++BeginItr) {
MachineInstr *MI = BeginItr;
-
- this->initPacketizerState();
+ initPacketizerState();
// End the current packet if needed.
- if (this->isSoloInstruction(MI)) {
+ if (isSoloInstruction(MI)) {
endPacket(MBB, MI);
continue;
}
// Ignore pseudo instructions.
- if (this->ignorePseudoInstruction(MI, MBB))
+ if (ignorePseudoInstruction(MI, MBB))
continue;
SUnit *SUI = MIToSUnit[MI];
@@ -241,22 +242,20 @@ void VLIWPacketizerList::PacketizeMIs(Ma
bool ResourceAvail = ResourceTracker->canReserveResources(MI);
if (ResourceAvail && shouldAddToPacket(MI)) {
// Dependency check for MI with instructions in CurrentPacketMIs.
- for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
- VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
- MachineInstr *MJ = *VI;
+ for (auto MJ : CurrentPacketMIs) {
SUnit *SUJ = MIToSUnit[MJ];
assert(SUJ && "Missing SUnit Info!");
// Is it legal to packetize SUI and SUJ together.
- if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {
+ if (!isLegalToPacketizeTogether(SUI, SUJ)) {
// Allow packetization if dependency can be pruned.
- if (!this->isLegalToPruneDependencies(SUI, SUJ)) {
+ if (!isLegalToPruneDependencies(SUI, SUJ)) {
// End the packet if dependency cannot be pruned.
endPacket(MBB, MI);
break;
- } // !isLegalToPruneDependencies.
- } // !isLegalToPacketizeTogether.
- } // For all instructions in CurrentPacketMIs.
+ }
+ }
+ }
} else {
// End the packet if resource is not available, or if the instruction
// shoud not be added to the current packet.
@@ -264,8 +263,8 @@ void VLIWPacketizerList::PacketizeMIs(Ma
}
// Add MI to the current packet.
- BeginItr = this->addToPacket(MI);
- } // For all instructions in BB.
+ BeginItr = addToPacket(MI);
+ } // For all instructions in the packetization range.
// End any packet left behind.
endPacket(MBB, EndItr);
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