[PATCH] D16126: LiveInterval: Add utility class to rename independent subregister usage

[Matthias Braun via llvm-commits]

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This supersedes http://reviews.llvm.org/D14966

This renaming is necessary to avoid a subregister aware scheduler
accidentally creating liveness "holes" which are rejected by the
MachineVerifier.

Explanation as found in this patch:

Helper class that can divide MachineOperands of a virtual register into
equivalence classes of connected components.
MachineOperands belong to the same equivalence class when they are part of
the same SubRange segment or adjacent segments (adjacent in control
flow); Different subranges affected by the same MachineOperand belong to
the same equivalence class.

Example:
  vreg0:sub0 = ...
  vreg0:sub1 = ...
  vreg0:sub2 = ...
  ...
  xxx        = op vreg0:sub1
  vreg0:sub1 = ...
  store vreg0:sub0_sub1

The example contains 3 different equivalence classes:
  - One for the (dead) vreg0:sub2 definition
  - One containing the first vreg0:sub1 definition and its use,
    but not the second definition!
  - The remaining class contains all other operands involving vreg0.

We provide a utility function here to rename disjunct classes to different
virtual registers.

Repository:
  rL LLVM

http://reviews.llvm.org/D16126

Files:
  include/llvm/CodeGen/LiveInterval.h
  include/llvm/CodeGen/LiveIntervalAnalysis.h
  lib/CodeGen/LiveInterval.cpp
  lib/CodeGen/LiveIntervalAnalysis.cpp

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