[PATCH] D16067: Redundant vmov instruction generated with vcvtph2ps

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL257470: The isel pattern that selects the memory-register form of VCVTPH2PS (authored by rlougher).

Changed prior to commit:
  http://reviews.llvm.org/D16067?vs=44509&id=44617#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D16067

Files:
  llvm/trunk/lib/Target/X86/X86InstrSSE.td
  llvm/trunk/test/CodeGen/X86/f16c-intrinsics.ll

Index: llvm/trunk/lib/Target/X86/X86InstrSSE.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td
@@ -8257,6 +8257,9 @@
             (VCVTPH2PSrm addr:$src)>;
   def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
             (VCVTPH2PSrm addr:$src)>;
+  def : Pat<(int_x86_vcvtph2ps_128 (bitconvert
+              (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
+            (VCVTPH2PSrm addr:$src)>;
 
   def : Pat<(store (f64 (extractelt (bc_v2f64 (v8i16
                   (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
Index: llvm/trunk/test/CodeGen/X86/f16c-intrinsics.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/f16c-intrinsics.ll
+++ llvm/trunk/test/CodeGen/X86/f16c-intrinsics.ll
@@ -61,6 +61,18 @@
   ret <4 x float> %res
 }
 
+define <4 x float> @test_x86_vcvtps2ph_128_scalar2(i64* %ptr) {
+; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar2:
+; CHECK-NOT: vmov
+; CHECK: vcvtph2ps (%
+
+  %load = load i64, i64* %ptr
+  %ins = insertelement <2 x i64> undef, i64 %load, i32 0
+  %bc = bitcast <2 x i64> %ins to <8 x i16>
+  %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc)
+  ret <4 x float> %res
+}
+
 define void @test_x86_vcvtps2ph_256_m(<8 x i16>* nocapture %d, <8 x float> %a) nounwind {
 entry:
   ; CHECK-LABEL: test_x86_vcvtps2ph_256_m:


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