[PATCH] D16061: [Utils] Insert DW_OP_bit_piece when only describing part of the variable

[Adrian Prantl via llvm-commits]

aprantl added inline comments.

================
Comment at: lib/Transforms/Utils/Local.cpp:1061
@@ +1060,3 @@
+    const DataLayout &DL = DDI->getModule()->getDataLayout();
+    NewDIExpr.push_back(DL.getTypeSizeInBits(ExtendedArg->getType())); // Size
+    Builder.insertDbgValueIntrinsic(ExtendedArg, 0, DIVar,
----------------
It's not clear to me that a sign/zero-extended value always indicates that the value is a subset of the variable. Is that guaranteed? Note that the Verifier checks that a piece does not cover the entire variable.

================
Comment at: test/Transforms/Util/split-bit-piece.ll:1
@@ +1,2 @@
+; Checks that SROA inserts a proper bit piece expression if it only describes
+; part of a variable
----------------
SORA can create bit pieces, but in this case I assume it's Local that is supposed to generate the bit piece?

================
Comment at: test/Transforms/Util/split-bit-piece.ll:14
@@ +13,3 @@
+  %v2 = alloca i64, align 8
+  store i32 %hs, i32* %hs.addr, align 4
+; CHECK: call void @llvm.dbg.value({{[^,]*}}, i64 0, metadata !{{[0-9]+}}, metadata ![[EXPR:[0-9]+]])
----------------
Please also check for the fist argument of the dbg.value so it is clear what the assumptions about the lowering are. This will help us keeping the test useful in the future.


Repository:
  rL LLVM

http://reviews.llvm.org/D16061