[llvm] r257184 - Do not ASSERTZEXT for i16 result of bitcast from f16 operand
Pirama Arumuga Nainar via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 8 09:46:05 PST 2016
Author: pirama
Date: Fri Jan 8 11:46:05 2016
New Revision: 257184
URL: http://llvm.org/viewvc/llvm-project?rev=257184&view=rev
Log:
Do not ASSERTZEXT for i16 result of bitcast from f16 operand
Summary:
During legalization if i16, do not ASSERTZEXT the result of FP_TO_FP16.
Directly return an FP_TO_FP16 node with return type as the
promote-to-type of i16.
This patch also removes extraneous length check. This legalization
should be valid even if integer and float types are of different
lengths.
This patch breaks a hard-float test for fp16 args. The test is changed
to allow a vmov to zero-out the top bits, and also ensure that the
return value is in an FP register.
Reviewers: ab, jmolloy
Subscribers: srhines, llvm-commits
Differential Revision: http://reviews.llvm.org/D15438
Added:
llvm/trunk/test/CodeGen/ARM/fp16-v3.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/test/CodeGen/ARM/fp16-args.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=257184&r1=257183&r2=257184&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Jan 8 11:46:05 2016
@@ -262,12 +262,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
case TargetLowering::TypePromoteFloat: {
// Convert the promoted float by hand.
- if (NOutVT.bitsEq(NInVT)) {
- SDValue PromotedOp = GetPromotedFloat(InOp);
- SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
- return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
- DAG.getValueType(OutVT));
- }
+ SDValue PromotedOp = GetPromotedFloat(InOp);
+ return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
break;
}
case TargetLowering::TypeExpandInteger:
Modified: llvm/trunk/test/CodeGen/ARM/fp16-args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-args.ll?rev=257184&r1=257183&r2=257184&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-args.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-args.ll Fri Jan 8 11:46:05 2016
@@ -32,9 +32,10 @@ entry:
; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1
; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0
; HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
-; HARD: vcvtb.f16.f32 s0, {{s[0-9]+}}
-; HARD-NOT: vmov
-; HARD-NOT: uxth
+; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
+; HARD-NEXT: vmov [[REG0:r[0-9]+]], [[SREG]]
+; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
+; HARD-NEXT: vmov s0, [[REG1]]
; CHECK: bx lr
}
Added: llvm/trunk/test/CodeGen/ARM/fp16-v3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-v3.ll?rev=257184&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-v3.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fp16-v3.ll Fri Jan 8 11:46:05 2016
@@ -0,0 +1,28 @@
+; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7a--none-eabi"
+
+; CHECK-LABEL: test_vec3:
+; CHECK: vcvtb.f32.f16
+; CHECK: vcvt.f32.s32
+; CHECK: vadd.f32
+; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}}
+; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]]
+; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]]
+; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16
+; CHECK-DAG: strh [[RREG1]], [r0, #4]
+; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
+; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
+; CHECK-NEXT: bx lr
+define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
+ %H = sitofp i32 %i to half
+ %S = fadd half %H, 0xH4A00
+ %1 = insertelement <3 x half> undef, half %S, i32 0
+ %2 = insertelement <3 x half> %1, half %S, i32 1
+ %3 = insertelement <3 x half> %2, half %S, i32 2
+ store <3 x half> %3, <3 x half>* %arr, align 8
+ ret void
+}
+
+attributes #0 = { nounwind }
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