[PATCH] D15932: RBIT Instruction only available for ARMv6t2 and above.

[Z. Zheng via llvm-commits]

zzheng updated the summary for this revision.
zzheng updated this revision to Diff 44300.
zzheng added a comment.

Thanks James. Totally missed legalization part. Please review the new patch.


Repository:
  rL LLVM

http://reviews.llvm.org/D15932

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/bit-reverse-to-rbit.ll

Index: test/CodeGen/ARM/bit-reverse-to-rbit.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/bit-reverse-to-rbit.ll
@@ -0,0 +1,34 @@
+;RUN: opt -instcombine -S < %s | llc -mtriple=armv5e--linux-gnueabi | FileCheck %s
+;RUN: opt -instcombine -S < %s | llc -mtriple=thumbv4t--linux-gnueabi | FileCheck %s
+;RUN: opt -instcombine -S < %s | llc -mtriple=armv6--linux-gnueabi | FileCheck %s
+
+;RUN: opt -instcombine -S < %s | llc -mtriple=armv7--linux-gnueabi | FileCheck %s --check-prefix=RBIT
+;RUN: opt -instcombine -S < %s | llc -mtriple=thumbv8--linux-gnueabi | FileCheck %s --check-prefix=RBIT
+
+;CHECK-NOT: rbit
+;RBIT: rbit
+
+define void @byte_reversal(i8* %p, i32 %n) {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %cmp = icmp ult i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = sext i32 %i.0 to i64
+  %arrayidx = getelementptr inbounds i8, i8* %p, i64 %0
+  %1 = load i8, i8* %arrayidx, align 1
+  %or19 = call i8 @llvm.bitreverse.i8(i8 %1)
+  store i8 %or19, i8* %arrayidx, align 1
+  %inc = add i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare i8 @llvm.bitreverse.i8(i8)
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -744,7 +744,7 @@
     setOperationAction(ISD::SUBE,    MVT::i32, Custom);
   }
 
-  if (!Subtarget->isThumb1Only())
+  if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
     setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
 
   // ARM does not have ROTL.


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