[llvm] r257033 - [X86] Add OpSize32 to MOVSX32_NOREX instructions to match their other versions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 6 22:37:53 PST 2016
Author: ctopper
Date: Thu Jan 7 00:37:52 2016
New Revision: 257033
URL: http://llvm.org/viewvc/llvm-project?rev=257033&view=rev
Log:
[X86] Add OpSize32 to MOVSX32_NOREX instructions to match their other versions.
Modified:
llvm/trunk/lib/Target/X86/X86InstrExtension.td
Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=257033&r1=257032&r2=257033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Thu Jan 7 00:37:52 2016
@@ -98,22 +98,22 @@ let hasSideEffects = 0, isCodeGenOnly =
def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
(outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
"movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
- [], IIC_MOVZX>, TB, Sched<[WriteALU]>;
+ [], IIC_MOVZX>, TB, OpSize32, Sched<[WriteALU]>;
let mayLoad = 1 in
def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
(outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
"movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
- [], IIC_MOVZX>, TB, Sched<[WriteALULd]>;
+ [], IIC_MOVZX>, TB, OpSize32, Sched<[WriteALULd]>;
def MOVSX32_NOREXrr8 : I<0xBE, MRMSrcReg,
(outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
"movs{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
- [], IIC_MOVSX>, TB, Sched<[WriteALU]>;
+ [], IIC_MOVSX>, TB, OpSize32, Sched<[WriteALU]>;
let mayLoad = 1 in
def MOVSX32_NOREXrm8 : I<0xBE, MRMSrcMem,
(outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
"movs{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
- [], IIC_MOVSX>, TB, Sched<[WriteALULd]>;
+ [], IIC_MOVSX>, TB, OpSize32, Sched<[WriteALULd]>;
}
// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
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