[llvm] r256454 - [x86] lower calls to llvm.maxnum.v4f32 using maxps
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 26 13:44:56 PST 2015
Author: spatel
Date: Sat Dec 26 15:44:55 2015
New Revision: 256454
URL: http://llvm.org/viewvc/llvm-project?rev=256454&view=rev
Log:
[x86] lower calls to llvm.maxnum.v4f32 using maxps
This is a follow-on to:
http://reviews.llvm.org/rL255700
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/fmaxnum.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=256454&r1=256453&r2=256454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Dec 26 15:44:55 2015
@@ -26866,20 +26866,22 @@ static SDValue PerformFMinFMaxCombine(SD
static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget) {
- // This takes at least 3 instructions, so favor a library call when
- // minimizing code size.
- if (DAG.getMachineFunction().getFunction()->optForMinSize())
+ if (Subtarget->useSoftFloat())
return SDValue();
- EVT VT = N->getValueType(0);
-
// TODO: Check for global or instruction-level "nnan". In that case, we
// should be able to lower to FMAX/FMIN alone.
// TODO: If an operand is already known to be a NaN or not a NaN, this
// should be an optional swap and FMAX/FMIN.
// TODO: Allow f64, vectors, and fminnum.
- if (VT != MVT::f32 || !Subtarget->hasSSE1() || Subtarget->useSoftFloat())
+ EVT VT = N->getValueType(0);
+ if (!(Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)))
+ return SDValue();
+
+ // This takes at least 3 instructions, so favor a library call when operating
+ // on a scalar and minimizing code size.
+ if (!VT.isVector() && DAG.getMachineFunction().getFunction()->optForMinSize())
return SDValue();
SDValue Op0 = N->getOperand(0);
@@ -26911,7 +26913,8 @@ static SDValue performFMaxNumCombine(SDN
// If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands
// are NaN, the NaN value of Op1 is the result.
- return DAG.getNode(ISD::SELECT, DL, VT, IsOp0Nan, Op1, Max);
+ auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
+ return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, Max);
}
/// Do target-specific dag combines on X86ISD::FAND nodes.
Modified: llvm/trunk/test/CodeGen/X86/fmaxnum.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fmaxnum.ll?rev=256454&r1=256453&r2=256454&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fmaxnum.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fmaxnum.ll Sat Dec 26 15:44:55 2015
@@ -94,151 +94,36 @@ define x86_fp80 @test_intrinsic_fmaxl(x8
ret x86_fp80 %z
}
-; FIXME: This should not be doing 4 scalar ops on a 2 element vector.
-; FIXME: This should use vector ops (maxps / cmpps).
-
; CHECK-LABEL: @test_intrinsic_fmax_v2f32
; SSE: movaps %xmm1, %xmm2
-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,1,2,3]
-; SSE-NEXT: movaps %xmm0, %xmm3
-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
-; SSE-NEXT: movaps %xmm3, %xmm4
-; SSE-NEXT: cmpunordss %xmm4, %xmm4
-; SSE-NEXT: movaps %xmm4, %xmm5
-; SSE-NEXT: andps %xmm2, %xmm5
-; SSE-NEXT: maxss %xmm3, %xmm2
-; SSE-NEXT: andnps %xmm2, %xmm4
-; SSE-NEXT: orps %xmm5, %xmm4
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
-; SSE-NEXT: movaps %xmm0, %xmm5
-; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1,2,3]
-; SSE-NEXT: movaps %xmm5, %xmm3
-; SSE-NEXT: cmpunordss %xmm3, %xmm3
-; SSE-NEXT: movaps %xmm3, %xmm6
-; SSE-NEXT: andps %xmm2, %xmm6
-; SSE-NEXT: maxss %xmm5, %xmm2
-; SSE-NEXT: andnps %xmm2, %xmm3
-; SSE-NEXT: orps %xmm6, %xmm3
-; SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: cmpunordss %xmm2, %xmm2
-; SSE-NEXT: movaps %xmm2, %xmm4
-; SSE-NEXT: andps %xmm1, %xmm4
-; SSE-NEXT: movaps %xmm1, %xmm5
-; SSE-NEXT: maxss %xmm0, %xmm5
-; SSE-NEXT: andnps %xmm5, %xmm2
-; SSE-NEXT: orps %xmm4, %xmm2
-; SSE-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
-; SSE-NEXT: shufpd {{.*#+}} xmm0 = xmm0[1,0]
-; SSE-NEXT: movapd %xmm0, %xmm4
-; SSE-NEXT: cmpunordss %xmm4, %xmm4
-; SSE-NEXT: movaps %xmm4, %xmm5
-; SSE-NEXT: andps %xmm1, %xmm5
-; SSE-NEXT: maxss %xmm0, %xmm1
-; SSE-NEXT: andnps %xmm1, %xmm4
-; SSE-NEXT: orps %xmm5, %xmm4
-; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
-; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: maxps %xmm0, %xmm2
+; SSE-NEXT: cmpunordps %xmm0, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm1
+; SSE-NEXT: andnps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
-; AVX: vmaxss %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm1, %xmm2, %xmm2
-; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT: vmovshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
-; AVX-NEXT: vmaxss %xmm3, %xmm4, %xmm5
-; AVX-NEXT: vcmpunordss %xmm3, %xmm3, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3]
-; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
-; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm1[1,0]
-; AVX-NEXT: vmaxss %xmm3, %xmm4, %xmm5
-; AVX-NEXT: vcmpunordss %xmm3, %xmm3, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
-; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
-; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
-; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm3
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm3, %xmm0
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
+; AVX: vmaxps %xmm0, %xmm1, %xmm2
+; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; AVX-NEXT: retq
define <2 x float> @test_intrinsic_fmax_v2f32(<2 x float> %x, <2 x float> %y) {
%z = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
ret <2 x float> %z
}
-; FIXME: This should use vector ops (maxps / cmpps).
-
; CHECK-LABEL: @test_intrinsic_fmax_v4f32
; SSE: movaps %xmm1, %xmm2
-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,1,2,3]
-; SSE-NEXT: movaps %xmm0, %xmm3
-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
-; SSE-NEXT: movaps %xmm3, %xmm4
-; SSE-NEXT: cmpunordss %xmm4, %xmm4
-; SSE-NEXT: movaps %xmm4, %xmm5
-; SSE-NEXT: andps %xmm2, %xmm5
-; SSE-NEXT: maxss %xmm3, %xmm2
-; SSE-NEXT: andnps %xmm2, %xmm4
-; SSE-NEXT: orps %xmm5, %xmm4
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
-; SSE-NEXT: movaps %xmm0, %xmm5
-; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1,2,3]
-; SSE-NEXT: movaps %xmm5, %xmm3
-; SSE-NEXT: cmpunordss %xmm3, %xmm3
-; SSE-NEXT: movaps %xmm3, %xmm6
-; SSE-NEXT: andps %xmm2, %xmm6
-; SSE-NEXT: maxss %xmm5, %xmm2
-; SSE-NEXT: andnps %xmm2, %xmm3
-; SSE-NEXT: orps %xmm6, %xmm3
-; SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: cmpunordss %xmm2, %xmm2
-; SSE-NEXT: movaps %xmm2, %xmm4
-; SSE-NEXT: andps %xmm1, %xmm4
-; SSE-NEXT: movaps %xmm1, %xmm5
-; SSE-NEXT: maxss %xmm0, %xmm5
-; SSE-NEXT: andnps %xmm5, %xmm2
-; SSE-NEXT: orps %xmm4, %xmm2
-; SSE-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
-; SSE-NEXT: shufpd {{.*#+}} xmm0 = xmm0[1,0]
-; SSE-NEXT: movapd %xmm0, %xmm4
-; SSE-NEXT: cmpunordss %xmm4, %xmm4
-; SSE-NEXT: movaps %xmm4, %xmm5
-; SSE-NEXT: andps %xmm1, %xmm5
-; SSE-NEXT: maxss %xmm0, %xmm1
-; SSE-NEXT: andnps %xmm1, %xmm4
-; SSE-NEXT: orps %xmm5, %xmm4
-; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
-; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: maxps %xmm0, %xmm2
+; SSE-NEXT: cmpunordps %xmm0, %xmm0
+; SSE-NEXT: andps %xmm0, %xmm1
+; SSE-NEXT: andnps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
-; AVX: vmaxss %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm1, %xmm2, %xmm2
-; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT: vmovshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
-; AVX-NEXT: vmaxss %xmm3, %xmm4, %xmm5
-; AVX-NEXT: vcmpunordss %xmm3, %xmm3, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3]
-; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
-; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm1[1,0]
-; AVX-NEXT: vmaxss %xmm3, %xmm4, %xmm5
-; AVX-NEXT: vcmpunordss %xmm3, %xmm3, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
-; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
-; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
-; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm3
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm3, %xmm0
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
+; AVX: vmaxps %xmm0, %xmm1, %xmm2
+; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; AVX-NEXT: retq
define <4 x float> @test_intrinsic_fmax_v4f32(<4 x float> %x, <4 x float> %y) {
%z = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
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