[llvm] r256362 - AMDGPU: Fix getRegisterBitWidth for vectors
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 23 21:14:55 PST 2015
Author: arsenm
Date: Wed Dec 23 23:14:55 2015
New Revision: 256362
URL: http://llvm.org/viewvc/llvm-project?rev=256362&view=rev
Log:
AMDGPU: Fix getRegisterBitWidth for vectors
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp?rev=256362&r1=256361&r2=256362&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp Wed Dec 23 23:14:55 2015
@@ -74,7 +74,9 @@ unsigned AMDGPUTTIImpl::getNumberOfRegis
return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
}
-unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; }
+unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
+ return Vector ? 0 : 32;
+}
unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
// Semi-arbitrary large amount.
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