[PATCH] D15702: [AArch64] Optimize some simple TBZ/TBNZ cases.

[Chad Rosier via llvm-commits]

mcrosier added inline comments.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:9528
@@ +9527,3 @@
+  case ISD::AND:
+    if ((C->getZExtValue() >> Bit) & 1) {
+      return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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Please remove the extra curly brackets.

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:9534
@@ +9533,3 @@
+  // (tbz (shl x, c), b) -> (tbz x, b-c)
+  case ISD::SHL:
+    if (C->getZExtValue() <= Bit &&
----------------
Mind adding a test that covers this case?

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:9543
@@ +9542,3 @@
+  // (tbz (shr x, c), b) -> (tbz x, b+c)
+  case ISD::SRA:
+  case ISD::SRL:
----------------
I don't think SRA is covered by a test.  If so, please add one.


http://reviews.llvm.org/D15702