[llvm] r256158 - [AArch64] Enable PostRAScheduler for AArch64 generic build.
Chad Rosier via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 21 06:43:47 PST 2015
Author: mcrosier
Date: Mon Dec 21 08:43:45 2015
New Revision: 256158
URL: http://llvm.org/viewvc/llvm-project?rev=256158&view=rev
Log:
[AArch64] Enable PostRAScheduler for AArch64 generic build.
Disable post-ra scheduler for perturbed tests to appease the bots and to
preserve the history of the tests.
http://reviews.llvm.org/D15652
Modified:
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
llvm/trunk/test/CodeGen/AArch64/alloca.ll
llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll
llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll
llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll
llvm/trunk/test/CodeGen/AArch64/arm64-large-frame.ll
llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
llvm/trunk/test/CodeGen/AArch64/arm64-trunc-store.ll
llvm/trunk/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
llvm/trunk/test/CodeGen/AArch64/arm64-xaluo.ll
llvm/trunk/test/CodeGen/AArch64/atomic-ops.ll
llvm/trunk/test/CodeGen/AArch64/bitcast-v2i8.ll
llvm/trunk/test/CodeGen/AArch64/dag-combine-select.ll
llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/global-merge-3.ll
llvm/trunk/test/CodeGen/AArch64/nest-register.ll
llvm/trunk/test/CodeGen/AArch64/nontemporal.ll
llvm/trunk/test/CodeGen/AArch64/tailcall-explicit-sret.ll
llvm/trunk/test/CodeGen/AArch64/vector-fcopysign.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Mon Dec 21 08:43:45 2015
@@ -102,7 +102,7 @@ public:
const Triple &getTargetTriple() const { return TargetTriple; }
bool enableMachineScheduler() const override { return true; }
bool enablePostRAScheduler() const override {
- return isCortexA53() || isCortexA57();
+ return isGeneric() || isCortexA53() || isCortexA57();
}
bool hasV8_1aOps() const { return HasV8_1aOps; }
@@ -139,6 +139,7 @@ public:
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
+ bool isGeneric() const { return CPUString == "generic"; }
bool isCyclone() const { return CPUString == "cyclone"; }
bool isCortexA57() const { return CPUString == "cortex-a57"; }
bool isCortexA53() const { return CPUString == "cortex-a53"; }
Modified: llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -disable-post-ra < %s | FileCheck %s
; This test aims to check basic correctness of frame layout &
; frame access code. There are 8 functions in this test file,
Modified: llvm/trunk/test/CodeGen/AArch64/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/alloca.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/alloca.ll Mon Dec 21 08:43:45 2015
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
+; RUN: llc -mtriple=aarch64-linux-gnu -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
declare void @use_addr(i8*)
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s
@var = global i32 0, align 4
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll Mon Dec 21 08:43:45 2015
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -disable-post-ra | FileCheck %s --check-prefix=CHECK-LINUX
; CHECK-LABEL: main:
; CHECK: stp x29, x30, [sp, #-16]!
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios7.0 -disable-post-ra -o - %s | FileCheck %s
@ptr = global i8* null
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -no-integrated-as | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -no-integrated-as -disable-post-ra | FileCheck %s
; rdar://9167275
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-large-frame.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-large-frame.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-large-frame.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-large-frame.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -disable-fp-elim < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -disable-fp-elim -disable-post-ra < %s | FileCheck %s
declare void @use_addr(i8*)
@addr = global i8* null
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-shrink-wrapping.ll Mon Dec 21 08:43:45 2015
@@ -1,5 +1,5 @@
-; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
-; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
+; RUN: llc %s -o - -enable-shrink-wrap=true -disable-post-ra | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
+; RUN: llc %s -o - -enable-shrink-wrap=false -disable-post-ra | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios"
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-trunc-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-trunc-store.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-trunc-store.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-trunc-store.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra | FileCheck %s
define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind {
; CHECK-LABEL: bar:
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-variadic-aapcs.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-variadic-aapcs.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-variadic-aapcs.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s
%va_list = type {i8*, i8*, i8*, i32, i32}
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-xaluo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-xaluo.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-xaluo.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-xaluo.ll Mon Dec 21 08:43:45 2015
@@ -1,5 +1,5 @@
-; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
;
; Get the actual value of the overflow bit.
Modified: llvm/trunk/test/CodeGen/AArch64/atomic-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/atomic-ops.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/atomic-ops.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/atomic-ops.ll Mon Dec 21 08:43:45 2015
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
-; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
Modified: llvm/trunk/test/CodeGen/AArch64/bitcast-v2i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitcast-v2i8.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bitcast-v2i8.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bitcast-v2i8.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-apple-ios | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck %s
; Part of PR21549: going through the stack isn't ideal but is correct.
Modified: llvm/trunk/test/CodeGen/AArch64/dag-combine-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/dag-combine-select.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/dag-combine-select.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/dag-combine-select.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -o - %s | FileCheck %s
+; RUN: llc -disable-post-ra -o - %s | FileCheck %s
target triple = "arm64--"
@out = internal global i32 0, align 4
Modified: llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
Modified: llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll Mon Dec 21 08:43:45 2015
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-post-ra | FileCheck --check-prefix=CHECK %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -disable-post-ra | FileCheck --check-prefix=CHECK-NOFP %s
%myStruct = type { i64 , i8, i32 }
Modified: llvm/trunk/test/CodeGen/AArch64/global-merge-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/global-merge-3.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/global-merge-3.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/global-merge-3.ll Mon Dec 21 08:43:45 2015
@@ -1,6 +1,6 @@
-; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
+; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
@x = global [1000 x i32] zeroinitializer, align 1
@y = global [1000 x i32] zeroinitializer, align 1
Modified: llvm/trunk/test/CodeGen/AArch64/nest-register.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/nest-register.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/nest-register.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/nest-register.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -disable-post-ra -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register.
Modified: llvm/trunk/test/CodeGen/AArch64/nontemporal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/nontemporal.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/nontemporal.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/nontemporal.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false -disable-post-ra | FileCheck %s
define void @test_stnp_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 {
; CHECK-LABEL: test_stnp_v4i64:
Modified: llvm/trunk/test/CodeGen/AArch64/tailcall-explicit-sret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailcall-explicit-sret.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/tailcall-explicit-sret.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/tailcall-explicit-sret.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false -disable-post-ra | FileCheck %s
; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks.
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
Modified: llvm/trunk/test/CodeGen/AArch64/vector-fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/vector-fcopysign.ll?rev=256158&r1=256157&r2=256158&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/vector-fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/vector-fcopysign.ll Mon Dec 21 08:43:45 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false -disable-post-ra | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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