[polly] r256125 - [FIX] Schedule generation for block exiting multiple loops.

[Johannes Doerfert via llvm-commits]

Author: jdoerfert
Date: Sun Dec 20 11:12:22 2015
New Revision: 256125

URL: http://llvm.org/viewvc/llvm-project?rev=256125&view=rev
Log:
[FIX] Schedule generation for block exiting multiple loops.

  This fixes bug PR25604.

Added:
    polly/trunk/test/ScopInfo/complex-loop-nesting.ll
Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=256125&r1=256124&r2=256125&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Sun Dec 20 11:12:22 2015
@@ -3462,12 +3462,12 @@ void Scop::buildSchedule(
           combineInSequence(LSchedulePair.first, StmtSchedule);
     }
 
+    isl_schedule *LSchedule = LSchedulePair.first;
     unsigned NumVisited = LSchedulePair.second;
     while (L && NumVisited == L->getNumBlocks()) {
-      auto *LDomain = isl_schedule_get_domain(LSchedulePair.first);
+      auto *LDomain = isl_schedule_get_domain(LSchedule);
       if (auto *MUPA = mapToDimension(LDomain, LD + 1))
-        LSchedulePair.first =
-            isl_schedule_insert_partial_schedule(LSchedulePair.first, MUPA);
+        LSchedule = isl_schedule_insert_partial_schedule(LSchedule, MUPA);
 
       auto *PL = L->getParentLoop();
 
@@ -3476,17 +3476,18 @@ void Scop::buildSchedule(
       // parent loop. In the former case this conditional will be skipped, in
       // the latter case however we will break here as we do not build a domain
       // nor a schedule for a infinite loop.
-      assert(LoopSchedules.count(PL) || LSchedulePair.first == nullptr);
+      assert(LoopSchedules.count(PL) || LSchedule == nullptr);
       if (!LoopSchedules.count(PL))
         break;
 
       auto &PSchedulePair = LoopSchedules[PL];
-      PSchedulePair.first =
-          combineInSequence(PSchedulePair.first, LSchedulePair.first);
+      PSchedulePair.first = combineInSequence(PSchedulePair.first, LSchedule);
       PSchedulePair.second += NumVisited;
 
       L = PL;
+      LD--;
       NumVisited = PSchedulePair.second;
+      LSchedule = PSchedulePair.first;
     }
   }
 }

Added: polly/trunk/test/ScopInfo/complex-loop-nesting.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/complex-loop-nesting.ll?rev=256125&view=auto
==============================================================================
--- polly/trunk/test/ScopInfo/complex-loop-nesting.ll (added)
+++ polly/trunk/test/ScopInfo/complex-loop-nesting.ll Sun Dec 20 11:12:22 2015
@@ -0,0 +1,64 @@
+; RUN: opt %loadPolly -polly-scops -analyze < %s | FileCheck %s
+;
+; CHECK:      Stmt_for_body_outer
+; CHECK:            Domain :=
+; CHECK:                { Stmt_for_body_outer[i0] : i0 <= 257 and i0 >= 0 };
+; CHECK:            Schedule :=
+; CHECK:                { Stmt_for_body_outer[i0] -> [i0, 0, 0, 0] };
+; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
+; CHECK:                { Stmt_for_body_outer[i0] -> MemRef_A[i0] };
+; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]
+; CHECK:                { Stmt_for_body_outer[i0] -> MemRef_A[i0] };
+; CHECK:      Stmt_for_body
+; CHECK:            Domain :=
+; CHECK:                { Stmt_for_body[257, i1] : i1 <= 1025 and i1 >= 0; Stmt_for_body[i0, 0] : i0 <= 256 and i0 >= 0 };
+; CHECK:            Schedule :=
+; CHECK:                { Stmt_for_body[257, i1] -> [257, 1, i1, 0]; Stmt_for_body[i0, 0] -> [i0, 1, 0, 0] : i0 <= 256 };
+; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
+; CHECK:                { Stmt_for_body[i0, i1] -> MemRef_A[i1] };
+; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]
+; CHECK:                { Stmt_for_body[i0, i1] -> MemRef_A[i1] };
+; CHECK:      Stmt_for_inc
+; CHECK:            Domain :=
+; CHECK:                { Stmt_for_inc[257, i1] : i1 <= 1025 and i1 >= 0 };
+; CHECK:            Schedule :=
+; CHECK:                { Stmt_for_inc[i0, i1] -> [257, 1, i1, 1] };
+; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 0]
+; CHECK:                { Stmt_for_inc[i0, i1] -> MemRef_A[i1] };
+; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]
+; CHECK:                { Stmt_for_inc[i0, i1] -> MemRef_A[i1] }
+;
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
+
+define void @foo(i32* %A) {
+entry:
+  br label %for.body.outer
+
+for.body.outer:                                   ; preds = %for.body, %entry
+  %indvar = phi i32 [0, %entry], [%indvar.next, %for.body]
+  %addr = getelementptr i32, i32* %A, i32 %indvar
+  %val = load i32, i32* %addr
+  %indvar.next = add i32 %indvar, 1
+  store i32 %val, i32* %addr
+  br label %for.body
+
+for.body:                                         ; preds = %for.inc, %for.body.outer
+  %indvar.2 = phi i32 [0, %for.body.outer], [%indvar.2.next, %for.inc]
+  %addr.2 = getelementptr i32, i32* %A, i32 %indvar.2
+  %val.2  = load i32, i32* %addr.2
+  %indvar.2.next = add i32 %indvar.2, 1
+  store i32 %val.2, i32* %addr.2
+  %cond.1 = icmp sle i32 %indvar, 256
+  br i1 %cond.1, label %for.body.outer, label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %addr.3 = getelementptr i32, i32* %A, i32 %indvar.2
+  %val.3  = load i32, i32* %addr.3
+  store i32 %val.3, i32* %addr.3
+  %cond = icmp sle i32 %indvar.2, 1024
+  br i1 %cond, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.inc
+  ret void
+}