[llvm] r255570 - [X86] Add relaxtion logic for ADC instructions.

[Quentin Colombet via llvm-commits]

> On Dec 14, 2015, at 3:59 PM, Craig Topper <craig.topper at gmail.com> wrote:
> 
> What about SBB?

Good point, we likely have the same problem.

I’ve checked and it is the case.

Fixed in revision 255583.

Good catch!

Thanks,
Q.

> 
> On Mon, Dec 14, 2015 at 3:12 PM, Quentin Colombet via llvm-commits <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
> Author: qcolombet
> Date: Mon Dec 14 17:12:40 2015
> New Revision: 255570
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=255570&view=rev <http://llvm.org/viewvc/llvm-project?rev=255570&view=rev>
> Log:
> [X86] Add relaxtion logic for ADC instructions.
> 
> Prior to this patch, we would wrongly stick to the variant with imm8 encoding
> even when the relocation could not fit that size.
> 
> rdar://problem/23785506
> 
> Modified:
>     llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
>     llvm/trunk/test/MC/ELF/relax-arith.s
> 
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=255570&r1=255569&r2=255570&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=255570&r1=255569&r2=255570&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Mon Dec 14 17:12:40 2015
> @@ -204,6 +204,14 @@ static unsigned getRelaxedOpcodeArith(un
>    case X86::ADD64ri8: return X86::ADD64ri32;
>    case X86::ADD64mi8: return X86::ADD64mi32;
> 
> +   // ADC
> +  case X86::ADC16ri8: return X86::ADC16ri;
> +  case X86::ADC16mi8: return X86::ADC16mi;
> +  case X86::ADC32ri8: return X86::ADC32ri;
> +  case X86::ADC32mi8: return X86::ADC32mi;
> +  case X86::ADC64ri8: return X86::ADC64ri32;
> +  case X86::ADC64mi8: return X86::ADC64mi32;
> +
>      // SUB
>    case X86::SUB16ri8: return X86::SUB16ri;
>    case X86::SUB16mi8: return X86::SUB16mi;
> 
> Modified: llvm/trunk/test/MC/ELF/relax-arith.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith.s?rev=255570&r1=255569&r2=255570&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith.s?rev=255570&r1=255569&r2=255570&view=diff>
> ==============================================================================
> --- llvm/trunk/test/MC/ELF/relax-arith.s (original)
> +++ llvm/trunk/test/MC/ELF/relax-arith.s Mon Dec 14 17:12:40 2015
> @@ -123,3 +123,19 @@ bar:
>          .section push,"x"
>          pushw $foo
>          push  $foo
> +
> +// CHECK:      Disassembly of section adc:
> +// CHECK-NEXT: adc:
> +// CHECK-NEXT:   0: 66 81 d3 00 00                       adcw $0, %bx
> +// CHECK-NEXT:   5: 66 81 14 25 00 00 00 00 00 00        adcw $0, 0
> +// CHECK-NEXT:   f: 81 d3 00 00 00 00                    adcl $0, %ebx
> +// CHECK-NEXT:  15: 81 14 25 00 00 00 00 00 00 00 00     adcl $0, 0
> +// CHECK-NEXT:  20: 48 81 d3 00 00 00 00                 adcq $0, %rbx
> +// CHECK-NEXT:  27: 48 81 14 25 00 00 00 00 00 00 00 00  adcq $0, 0
> +        .section adc,"x"
> +        adc  $foo, %bx
> +        adcw $foo, bar
> +        adc  $foo, %ebx
> +        adcl $foo, bar
> +        adc  $foo, %rbx
> +        adcq $foo, bar
> 
> 
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> 
> 
> 
> -- 
> ~Craig

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