[polly] r255471 - Always treat scalar writes as MUST_WRITEs

Tobias Grosser via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 14 07:10:37 PST 2015


On 12/14/2015 09:52 AM, Johannes Doerfert via llvm-commits wrote:
>
> On 12/14, Michael Kruse wrote:
>> 2015-12-14 8:59 GMT+01:00 Johannes Doerfert <doerfert at cs.uni-saarland.de>:
>>> What about a case like this:
>>>
>>> b0:
>>>    br %non_affine %b1, %b2
>>>
>>> b1:
>>>    x = ..
>>>    br %b3
>>>
>>> b2:
>>>    y = ...
>>>    br %b3
>>>
>>> b3:
>>>    z = phi [b1, x], [b2, y]
>>>
>>> shouldn't the phiops write accesses to x and y be MAY_WRITEs in the
>>> non-affine region b0-b3 ?
>>>
>>> I don't think it matters much but I since we try to model it right now I
>>> wanted to ask.
>>
>> They are not modelled at all because they are used only within the
>> non-affine subregion. x and y cannot be used after and including b3
>> because b3 is not dominated by either b1 or b2. There is also no
>> "phiops" write to x nor y because these are not PHI nodes.
>>
>> If you think about the two PHI WRITE accesses ("at" br %b3), They will
>> be collapsed to one MustWriteAccess in DependenceInfo for the whole
>> statement.
> I'm talking about the modeling in the SCoP here. Are these two accesses
> may or must accesses? In the former case I don't see how they are
> collapsed, in the latter I wonder if that is what we want. My initial
> comment aimed at the latter case, thus that we now model the phiops
> write access as must and not may.

I just chatted with Michael. The semantics are not 100% correct, but 
most likely save. However, documenting them is likely not worth the 
effort. We reverted the patch in r255503.

Gruesse,
Tobias


>> The z.phiops will be written by one of the PHI WRITEs,
>> leaving no possibility that the write could be only conditional.
>> Otherwise the IR would not be well-formed.
>>
>> Hope this addresses your concerns.
>>
>> Michael
>>
>>
>>> On 12/13, Michael Kruse via llvm-commits wrote:
>>>> Author: meinersbur
>>>> Date: Sun Dec 13 16:10:32 2015
>>>> New Revision: 255471
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=255471&view=rev
>>>> Log:
>>>> Always treat scalar writes as MUST_WRITEs
>>>>
>>>> LLVM's IR guarantees that a value definition occurs before any use, and
>>>> also the value of a PHI must be one of the incoming values, "written"
>>>> in one of the incoming blocks. Hence, such writes are never conditional
>>>> in the context of a non-affine subregion.
>>>>
>>>> Modified:
>>>>      polly/trunk/lib/Analysis/ScopInfo.cpp
>>>>      polly/trunk/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
>>>>      polly/trunk/test/ScopInfo/intra-non-affine-stmt-phi-node.ll
>>>>      polly/trunk/test/ScopInfo/non_affine_region_2.ll
>>>>      polly/trunk/test/ScopInfo/non_affine_region_3.ll
>>>>      polly/trunk/test/ScopInfo/non_affine_region_4.ll
>>>>
>>>> Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=255471&r1=255470&r2=255471&view=diff
>>>> ==============================================================================
>>>> --- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
>>>> +++ polly/trunk/lib/Analysis/ScopInfo.cpp Sun Dec 13 16:10:32 2015
>>>> @@ -3885,8 +3885,12 @@ void ScopInfo::addMemoryAccess(BasicBloc
>>>>     Value *BaseAddr = BaseAddress;
>>>>     std::string BaseName = getIslCompatibleName("MemRef_", BaseAddr, "");
>>>>
>>>> -  bool isApproximated =
>>>> -      Stmt->isRegionStmt() && (Stmt->getRegion()->getEntry() != BB);
>>>> +  // The execution of a store is not guaranteed if not in the entry block of a
>>>> +  // subregion. However, scalar writes (llvm::Value definitions or one of a
>>>> +  // PHI's incoming values) must occur in well-formed IR code.
>>>> +  bool isApproximated = (Kind == ScopArrayInfo::MK_Array) &&
>>>> +                        Stmt->isRegionStmt() &&
>>>> +                        (Stmt->getRegion()->getEntry() != BB);
>>>>     if (isApproximated && Type == MemoryAccess::MUST_WRITE)
>>>>       Type = MemoryAccess::MAY_WRITE;
>>>>
>>>>
>>>> Modified: polly/trunk/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll?rev=255471&r1=255470&r2=255471&view=diff
>>>> ==============================================================================
>>>> --- polly/trunk/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll (original)
>>>> +++ polly/trunk/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll Sun Dec 13 16:10:32 2015
>>>> @@ -39,7 +39,7 @@
>>>>   ; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
>>>>   ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_smax[] };
>>>> -; CHECK:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK:            MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_2__phi[] };
>>>>   ; CHECK:            ReadAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:                [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_0[] };
>>>>
>>>> Modified: polly/trunk/test/ScopInfo/intra-non-affine-stmt-phi-node.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/intra-non-affine-stmt-phi-node.ll?rev=255471&r1=255470&r2=255471&view=diff
>>>> ==============================================================================
>>>> --- polly/trunk/test/ScopInfo/intra-non-affine-stmt-phi-node.ll (original)
>>>> +++ polly/trunk/test/ScopInfo/intra-non-affine-stmt-phi-node.ll Sun Dec 13 16:10:32 2015
>>>> @@ -10,9 +10,9 @@
>>>>   ; CHECK-NEXT:             { Stmt_loop__TO__backedge[i0] -> [i0, 0] };
>>>>   ; CHECK-NEXT:         MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK-NEXT:             { Stmt_loop__TO__backedge[i0] -> MemRef_merge__phi[] };
>>>> -; CHECK-NEXT:         MayWriteAccess :=   [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK-NEXT:         MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK-NEXT:             { Stmt_loop__TO__backedge[i0] -> MemRef_merge__phi[] };
>>>> -; CHECK-NEXT:         MayWriteAccess :=   [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK-NEXT:         MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK-NEXT:             { Stmt_loop__TO__backedge[i0] -> MemRef_merge__phi[] };
>>>>   ; CHECK-NEXT:   Stmt_backedge
>>>>   ; CHECK-NEXT:         Domain :=
>>>>
>>>> Modified: polly/trunk/test/ScopInfo/non_affine_region_2.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/non_affine_region_2.ll?rev=255471&r1=255470&r2=255471&view=diff
>>>> ==============================================================================
>>>> --- polly/trunk/test/ScopInfo/non_affine_region_2.ll (original)
>>>> +++ polly/trunk/test/ScopInfo/non_affine_region_2.ll Sun Dec 13 16:10:32 2015
>>>> @@ -35,7 +35,7 @@
>>>>   ; CHECK-NEXT:        { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
>>>>   ; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
>>>>   ; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
>>>> -; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK:         MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK-NEXT:        { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
>>>>   ; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
>>>>   ; CHECK-NOT:         { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
>>>>
>>>> Modified: polly/trunk/test/ScopInfo/non_affine_region_3.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/non_affine_region_3.ll?rev=255471&r1=255470&r2=255471&view=diff
>>>> ==============================================================================
>>>> --- polly/trunk/test/ScopInfo/non_affine_region_3.ll (original)
>>>> +++ polly/trunk/test/ScopInfo/non_affine_region_3.ll Sun Dec 13 16:10:32 2015
>>>> @@ -31,11 +31,11 @@
>>>>   ; CHECK:             { Stmt_bb3__TO__bb18[i0] -> [i0, 0] };
>>>>   ; CHECK:         ReadAccess := [Reduction Type: NONE] [Scalar: 0]
>>>>   ; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
>>>> -; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK:         MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
>>>> -; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK:         MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
>>>> -; CHECK:         MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK:         MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
>>>>   ; CHECK:         MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:             { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
>>>>
>>>> Modified: polly/trunk/test/ScopInfo/non_affine_region_4.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/non_affine_region_4.ll?rev=255471&r1=255470&r2=255471&view=diff
>>>> ==============================================================================
>>>> --- polly/trunk/test/ScopInfo/non_affine_region_4.ll (original)
>>>> +++ polly/trunk/test/ScopInfo/non_affine_region_4.ll Sun Dec 13 16:10:32 2015
>>>> @@ -39,7 +39,7 @@
>>>>   ; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_A[i0] };
>>>>   ; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_x[] };
>>>> -; CHECK:            MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>> +; CHECK:            MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_y__phi[] };
>>>>   ; CHECK:            MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]
>>>>   ; CHECK:                { Stmt_bb2__TO__bb7[i0] -> MemRef_y__phi[] };
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at lists.llvm.org
>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>>
>>> --
>>>
>>> Johannes Doerfert
>>> Researcher / PhD Student
>>>
>>> Compiler Design Lab (Prof. Hack)
>>> Saarland University, Computer Science
>>> Building E1.3, Room 4.31
>>>
>>> Tel. +49 (0)681 302-57521 : doerfert at cs.uni-saarland.de
>>> Fax. +49 (0)681 302-3065  : http://www.cdl.uni-saarland.de/people/doerfert
>
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