[llvm] r255395 - Revert rL255391: [X86ISelLowering] Add additional support for multiplication-to-shift conversion.
Chen Li via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 11 16:08:37 PST 2015
Author: chenli
Date: Fri Dec 11 18:08:37 2015
New Revision: 255395
URL: http://llvm.org/viewvc/llvm-project?rev=255395&view=rev
Log:
Revert rL255391: [X86ISelLowering] Add additional support for multiplication-to-shift conversion.
because it broke buildbot.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/imul.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=255395&r1=255394&r2=255395&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 11 18:08:37 2015
@@ -24738,11 +24738,9 @@ static SDValue PerformMulCombine(SDNode
MulAmt1 = 3;
MulAmt2 = MulAmt / 3;
}
-
- SDLoc DL(N);
- SDValue NewMul;
if (MulAmt2 &&
(isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
+ SDLoc DL(N);
if (isPowerOf2_64(MulAmt2) &&
!(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
@@ -24751,6 +24749,7 @@ static SDValue PerformMulCombine(SDNode
// is an add.
std::swap(MulAmt1, MulAmt2);
+ SDValue NewMul;
if (isPowerOf2_64(MulAmt1))
NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
@@ -24764,32 +24763,10 @@ static SDValue PerformMulCombine(SDNode
else
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
DAG.getConstant(MulAmt2, DL, VT));
- }
- if (!NewMul) {
- uint64_t MaxVal = VT == MVT::i64 ? UINT64_MAX : UINT32_MAX;
- assert(MulAmt != 0 && MulAmt != MaxVal &&
- "Both cases that could cause potential "
- "overflows should have already been handled.");
- if (isPowerOf2_64(MulAmt - 1))
- // (mul x, 2^N + 1) => (add (shl x, N), x)
- NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
- DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
- DAG.getConstant(Log2_64(MulAmt - 1), DL,
- MVT::i8)));
-
- else if (isPowerOf2_64(MulAmt + 1))
- // (mul x, 2^N - 1) => (sub (shl x, N), x)
- NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
- N->getOperand(0),
- DAG.getConstant(Log2_64(MulAmt + 1),
- DL, MVT::i8)), N->getOperand(0));
- }
-
- if (NewMul)
// Do not add new nodes to DAG combiner worklist.
DCI.CombineTo(N, NewMul, false);
-
+ }
return SDValue();
}
Modified: llvm/trunk/test/CodeGen/X86/imul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/imul.ll?rev=255395&r1=255394&r2=255395&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/imul.ll (original)
+++ llvm/trunk/test/CodeGen/X86/imul.ll Fri Dec 11 18:08:37 2015
@@ -126,48 +126,3 @@ define i32 @mul40_32_minsize(i32 %A) min
%mul = mul i32 %A, 40
ret i32 %mul
}
-
-define i32 @mul33_32(i32 %A) {
-; X64-LABEL: mul33_32:
-; X64: shll
-; X64-NEXT: leal
-; X86-LABEL: mul33_32:
-; X86: shll
-; X86-NEXT: addl
- %mul = mul i32 %A, 33
- ret i32 %mul
-}
-
-define i32 @mul31_32(i32 %A) {
-; X64-LABEL: mul31_32:
-; X64: shll
-; X64-NEXT: subl
-; X86-LABEL: mul31_32:
-; X86: shll
-; X86-NEXT: subl
- %mul = mul i32 %A, 31
- ret i32 %mul
-}
-
-define i32 @mul0_32(i32 %A) {
-; X64-LABEL: mul0_32:
-; X64: xorl %eax, %eax
- %mul = mul i32 %A, 0
- ret i32 %mul
-}
-
-define i32 @mul4294967295_32(i32 %A) {
-; X64-LABEL: mul4294967295_32:
-; X64: negl %edi
-; X64-NEXT: movl %edi, %eax
- %mul = mul i32 %A, 4294967295
- ret i32 %mul
-}
-
-define i64 @mul18446744073709551615_64(i64 %A) {
-; X64-LABEL: mul18446744073709551615_64:
-; X64: negq %rdi
-; X64-NEXT: movq %rdi, %rax
- %mul = mul i64 %A, 18446744073709551615
- ret i64 %mul
-}
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