[PATCH] D15397: [EarlyCSE] DSE of stores which write back loaded values

[JF Bastien via llvm-commits]

jfb added a comment.

Technically you could even remove `seq_cst` load/store pairs if they're not synchronizing with anything in the middle. You'd still have to preserve the effect with a fence, but the access is dead since it must have raced if it didn't synchronize with anything else.

Just to confirm (even though this optimization happens elsewhere): we don't care about memory accesses which normalize FP values, e.g. canonicalizing NaNs or flushing denormals to zero?


================
Comment at: test/Transforms/EarlyCSE/basic.ll:248
@@ +247,3 @@
+; location.  We do not have to respect the order in which those
+; writes were done.  
+define i32 @dse5(i32 *%P, i32 *%Q) {
----------------
Clarify: "that's okay because we're using relaxed memory ordering".


http://reviews.llvm.org/D15397