[PATCH] D14588: [X86][SSE] Transform truncation from v8i32/v16i32 to v8i8/v16i8 into bitand and X86ISD::PACKUS operations during DAG combine.

[Cong Hou via llvm-commits]

congh added inline comments.

================
Comment at: test/CodeGen/X86/vector-trunc.ll:240
@@ +239,3 @@
+  ret <8 x i8> %0
+}
+
----------------
RKSimon wrote:
> Please can you change this to a store <8 x i8> instead? Legalizing a <8 x i8> return means that its technically a <8 x i16> with undef upper bytes - which makes the truncation shuffle code hardware to track, especially on pre SSE41.
You are right. I have update this test case.


http://reviews.llvm.org/D14588