[llvm] r255113 - [AArch64] Fix FP16 vector instructions that should only accept low registers

[Oliver Stannard via llvm-commits]

Author: olista01
Date: Wed Dec  9 08:32:11 2015
New Revision: 255113

URL: http://llvm.org/viewvc/llvm-project?rev=255113&view=rev
Log:
[AArch64] Fix FP16 vector instructions that should only accept low registers

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
    llvm/trunk/test/MC/AArch64/fullfp16-diagnostics.s

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=255113&r1=255112&r2=255113&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Wed Dec  9 08:32:11 2015
@@ -6855,11 +6855,11 @@ multiclass SIMDFPIndexed<bit U, bits<4>
 
   let Predicates = [HasNEON, HasFullFP16] in {
   def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc,
-                                      FPR16Op, FPR16Op, V128, VectorIndexH,
+                                      FPR16Op, FPR16Op, V128_lo, VectorIndexH,
                                       asm, ".h", "", "", ".h",
     [(set (f16 FPR16Op:$Rd),
           (OpNode (f16 FPR16Op:$Rn),
-                  (f16 (vector_extract (v8f16 V128:$Rm),
+                  (f16 (vector_extract (v8f16 V128_lo:$Rm),
                                        VectorIndexH:$idx))))]> {
     bits<3> idx;
     let Inst{11} = idx{2};
@@ -6995,7 +6995,7 @@ multiclass SIMDFPIndexedTied<bit U, bits
 
   let Predicates = [HasNEON, HasFullFP16] in {
   def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc,
-                                      FPR16Op, FPR16Op, V128, VectorIndexH,
+                                      FPR16Op, FPR16Op, V128_lo, VectorIndexH,
                                       asm, ".h", "", "", ".h", []> {
     bits<3> idx;
     let Inst{11} = idx{2};

Modified: llvm/trunk/test/MC/AArch64/fullfp16-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/fullfp16-diagnostics.s?rev=255113&r1=255112&r2=255113&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/fullfp16-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/fullfp16-diagnostics.s Wed Dec  9 08:32:11 2015
@@ -40,3 +40,43 @@
 // CHECK:      error: invalid operand for instruction
 // CHECK-NEXT: fmulx v2.8h, v3.8h, v17.h[6]
 // CHECK-NEXT:                     ^
+
+  fmla h0, h1, v16.h[3]
+  fmla h2, h3, v17.h[6]
+
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmla h0, h1, v16.h[3]
+// CHECK-NEXT:              ^
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmla h2, h3, v17.h[6]
+// CHECK-NEXT:              ^
+
+  fmls h0, h1, v16.h[3]
+  fmls h2, h3, v17.h[6]
+
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmls h0, h1, v16.h[3]
+// CHECK-NEXT:              ^
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmls h2, h3, v17.h[6]
+// CHECK-NEXT:              ^
+
+  fmul h0, h1, v16.h[3]
+  fmul h2, h3, v17.h[6]
+
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmul h0, h1, v16.h[3]
+// CHECK-NEXT:              ^
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmul h2, h3, v17.h[6]
+// CHECK-NEXT:              ^
+
+  fmulx h0, h1, v16.h[3]
+  fmulx h2, h3, v17.h[6]
+
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmulx h0, h1, v16.h[3]
+// CHECK-NEXT:               ^
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: fmulx h2, h3, v17.h[6]
+// CHECK-NEXT:               ^