r255096 broke AMDGPU tests
Michel Dänzer via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 9 01:02:18 PST 2015
Hi Vikram,
your SVN r255096 broke 29 AMDGPU tests:
LLVM :: CodeGen/AMDGPU/basic-loop.ll
LLVM :: CodeGen/AMDGPU/ctpop.ll
LLVM :: CodeGen/AMDGPU/fma.ll
LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll
LLVM :: CodeGen/AMDGPU/lds-oqap-crash.ll
LLVM :: CodeGen/AMDGPU/lds-output-queue.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll
LLVM :: CodeGen/AMDGPU/load-i1.ll
LLVM :: CodeGen/AMDGPU/local-atomics.ll
LLVM :: CodeGen/AMDGPU/saddo.ll
LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested.ll
LLVM :: CodeGen/AMDGPU/schedule-fs-loop.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
LLVM :: CodeGen/AMDGPU/schedule-if.ll
LLVM :: CodeGen/AMDGPU/selectcc.ll
LLVM :: CodeGen/AMDGPU/setcc-opt.ll
LLVM :: CodeGen/AMDGPU/sext-eliminate.ll
LLVM :: CodeGen/AMDGPU/sext-in-reg.ll
LLVM :: CodeGen/AMDGPU/ssubo.ll
LLVM :: CodeGen/AMDGPU/uaddo.ll
LLVM :: CodeGen/AMDGPU/usubo.ll
I'm attaching the full output of the test failures.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
-------------- next part --------------
FAIL: LLVM :: CodeGen/AMDGPU/basic-loop.ll (1404 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/basic-loop.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=SI < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/basic-loop.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/basic-loop.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=tonga < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/basic-loop.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/basic-loop.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function test_loop: Post SSA
Frame Objects:
fi#0: size=8, align=4, at location [SP]
fi#1: size=8, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+16]
fi#3: size=4, align=4, at location [SP+20]
fi#4: size=8, align=4, at location [SP+24]
fi#5: size=4, align=4, at location [SP+32]
Function Live Ins: %SGPR0_SGPR1, %SGPR3
BB#0: derived from LLVM BB %entry
Live Ins: %SGPR0_SGPR1 %SGPR3 %VGPR3
%SGPR16<def> = S_MOV_B32 %SGPR3<kill>
%SGPR12<def> = S_MOV_B32 <es:SCRATCH_RSRC_DWORD0>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
%SGPR13<def> = S_MOV_B32 <es:SCRATCH_RSRC_DWORD1>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
%SGPR14<def> = S_MOV_B32 4294967295, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
%SGPR15<def> = S_MOV_B32 8450048, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 9; mem:LD8[undef(addrspace=2)](nontemporal)(invariant)
%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 13; mem:LD4[undef(addrspace=2)](nontemporal)(invariant)
%VGPR0<def,dead> = V_MOV_B32_e32 0, %EXEC<imp-use>
%VGPR0<def,dead> = V_MOV_B32_e32 0, %EXEC<imp-use>
%SGPR0_SGPR1<def> = S_MOV_B64 0
%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
S_WAITCNT 127
%VGPR3<def> = V_WRITELANE_B32_si %SGPR2, 0, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %SGPR3, 1, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %SGPR0, 2, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %SGPR1, 3, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %SGPR4, 4, %EXEC<imp-use>
BUFFER_STORE_DWORD_OFFSET %VGPR0, %SGPR12_SGPR13_SGPR14_SGPR15, %SGPR16, 20, 0, 0, 0, %EXEC<imp-use>, %VGPR0<imp-use>; mem:ST4[FixedStack3]
S_WAITCNT 1792
Successors according to CFG: BB#1(?%)
BB#1: derived from LLVM BB %loop.body
Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15 %SGPR16 %VGPR3
Predecessors according to CFG: BB#0 BB#1
%VGPR0<def> = BUFFER_LOAD_DWORD_OFFSET %SGPR12_SGPR13_SGPR14_SGPR15, %SGPR16, 20, 0, 0, 0, %EXEC<imp-use>, %VGPR0<imp-def>; mem:LD4[FixedStack3]
%SGPR0<def> = V_READLANE_B32_si %VGPR3, 2, %EXEC<imp-use>, %SGPR0_SGPR1<imp-def>
%SGPR1<def> = V_READLANE_B32_si %VGPR3, 3, %EXEC<imp-use>, %SGPR0_SGPR1<imp-def>
S_NOP 2
%SGPR2<def> = V_READLANE_B32_si %VGPR3, 0, %EXEC<imp-use>, %SGPR2_SGPR3<imp-def>
%SGPR3<def> = V_READLANE_B32_si %VGPR3, 1, %EXEC<imp-use>, %SGPR2_SGPR3<imp-def>
S_NOP 2
%SGPR4<def> = S_MOV_B32 %SGPR3
%SGPR5<def> = S_MOV_B32 %SGPR2
%SGPR6<def> = S_MOV_B32 61440
%SGPR7<def> = S_MOV_B32 -1
%SGPR8<def> = S_MOV_B32 %SGPR5<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
%SGPR9<def> = S_MOV_B32 %SGPR4<kill>
%SGPR10<def> = S_MOV_B32 %SGPR7<kill>
%SGPR11<def> = S_MOV_B32 %SGPR6<kill>
%VGPR1<def> = V_MOV_B32_e32 222, %EXEC<imp-use>
BUFFER_STORE_DWORD_OFFSET %VGPR1<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; mem:ST4[%out(addrspace=1)]
%SGPR4<def,dead> = S_MOV_B32 1
S_WAITCNT 1792
%VGPR1<def> = V_ADD_I32_e32 1, %VGPR0, %VCC<imp-def,dead>, %EXEC<imp-use>
%SGPR4<def> = V_READLANE_B32_si %VGPR3, 4, %EXEC<imp-use>, %SGPR4<imp-def>
S_NOP 2
%VGPR2<def,dead> = KILL %SGPR4
V_CMP_EQ_I32_e32 %SGPR4<kill>, %VGPR0<kill>, %VCC<imp-def>, %EXEC<imp-use>
%SGPR0_SGPR1<def> = S_OR_B64 %VCC, %SGPR0_SGPR1, %SCC<imp-def>
%VCC<def> = S_MOV_B64 %SGPR0_SGPR1
%VGPR3<def> = V_WRITELANE_B32_si %SGPR0, 6, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %SGPR1, 7, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %VCC_LO, 2, %EXEC<imp-use>
%VGPR3<def> = V_WRITELANE_B32_si %VCC_HI, 3, %EXEC<imp-use>
BUFFER_STORE_DWORD_OFFSET %VGPR1, %SGPR12_SGPR13_SGPR14_SGPR15, %SGPR16, 20, 0, 0, 0, %EXEC<imp-use>, %VGPR1<imp-use>; mem:ST4[FixedStack3]
S_WAITCNT 1792
%EXEC<def> = S_ANDN2_B64 %EXEC, %SGPR0_SGPR1, %SCC<imp-def>
S_CBRANCH_EXECNZ <BB#1>, %EXEC<imp-use>
Successors according to CFG: BB#2(0x04000000 / 0x80000000 = 3.12%) BB#1(0x7c000000 / 0x80000000 = 96.88%)
BB#2: derived from LLVM BB %end
Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15 %SGPR16 %VGPR3
Predecessors according to CFG: BB#1
%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1, %SCC<imp-def>
%SGPR0<def> = V_READLANE_B32_si %VGPR3, 6, %EXEC<imp-use>, %SGPR0_SGPR1<imp-def>
%SGPR1<def> = V_READLANE_B32_si %VGPR3, 7, %EXEC<imp-use>, %SGPR0_SGPR1<imp-def>
S_NOP 2
%SGPR2<def> = V_READLANE_B32_si %VGPR3, 4, %EXEC<imp-use>, %SGPR2<imp-def>
S_NOP 2
%SGPR4<def> = V_READLANE_B32_si %VGPR3, 0, %EXEC<imp-use>, %SGPR4_SGPR5<imp-def>
%SGPR5<def> = V_READLANE_B32_si %VGPR3, 1, %EXEC<imp-use>, %SGPR4_SGPR5<imp-def>
S_NOP 2
S_ENDPGM
# End machine code for function test_loop.
*** Bad machine code: Using an undefined physical register ***
- function: test_loop
- basic block: BB#2 end (0xa77ad8)
- instruction: %EXEC<def> = S_OR_B64
- operand 2: %SGPR0_SGPR1
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/ctpop.ll (1432 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/ctpop.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function v_ctpop_add_chain_i32: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 12, 0, 0, 2, 0, 0, 0, 0, 1
CF_TC_EG 8, 0
CF_ALU 13, 0, 0, 2, 0, 0, 0, 0, 1
CF_TC_EG 10, 0
CF_ALU 14, 0, 0, 2, 0, 0, 0, 4, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
FETCH_CLAUSE 8
%T0_X<def,tied1> = VTX_READ_GLOBAL_32_eg %T0_X<kill,tied0>, 0; mem:LD4[%in1(addrspace=1)]
FETCH_CLAUSE 10
%T1_X<def,tied1> = VTX_READ_GLOBAL_32_eg %T1_X<kill,tied0>, 0; mem:LD4[%in0(addrspace=1)]
ALU_CLAUSE 12
%T0_X<def> = MOV 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 13
%T1_X<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 14
%T0_Z<def> = BCNT_INT 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = BCNT_INT 1, 0, 0, 0, %T1_X<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 2
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PV_Z<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function v_ctpop_add_chain_i32.
*** Bad machine code: Illegal physical register for instruction ***
- function: v_ctpop_add_chain_i32
- basic block: BB#0 (0x1914258)
- instruction: %T0_X<def> = ADD_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: v_ctpop_add_chain_i32
- basic block: BB#0 (0x1914258)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
LLVM ERROR: Found 2 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ctpop.ll:40:15: error: expected string not found in input
; FUNC-LABEL: {{^}}v_ctpop_add_chain_i32:
^
<stdin>:35:14: note: scanning from here
v_ctpop_i32: ; @v_ctpop_i32
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/fma.ll (1482 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/fma.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/fma.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/fma.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/fma.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/fma.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function fma_commute_mul_inline_imm_f32: Post SSA, not tracking liveness
Function Live Ins: %T0_X
BB#0: derived from LLVM BB %0
Live Ins: %T0_X
CF_ALU 10, 0, 0, 2, 0, 0, 0, 3, 1
CF_TC_EG 6, 1
CF_ALU 14, 0, 0, 2, 0, 0, 0, 4, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
FETCH_CLAUSE 6
%T1_X<def,tied1> = VTX_READ_GLOBAL_32_eg %T1_X<kill,tied0>, 0; mem:LD4[%in.b.gep(addrspace=1)]
%T0_X<def,tied1> = VTX_READ_GLOBAL_32_eg %T0_X<kill,tied0>, 0; mem:LD4[%in.a.gep(addrspace=1)]
ALU_CLAUSE 10
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 14
%T0_X<def> = FMA_eg 0, 0, %T0_X<kill>, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, %T1_X<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1073741824, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 1073741824, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function fma_commute_mul_inline_imm_f32.
*** Bad machine code: Illegal physical register for instruction ***
- function: fma_commute_mul_inline_imm_f32
- basic block: BB#0 (0x19e3a18)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: fma_commute_mul_inline_imm_f32
- basic block: BB#0 (0x19e3a18)
- instruction: %T1_X<def> = ADD_INT
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: fma_commute_mul_inline_imm_f32
- basic block: BB#0 (0x19e3a18)
- instruction: %T1_X<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 3 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/fma.ll:63:15: error: expected string not found in input
; FUNC-LABEL: @fma_commute_mul_inline_imm_f32
^
<stdin>:79:12: note: scanning from here
fma_v4f32: ; @fma_v4f32
^
<stdin>:79:14: note: possible intended match here
fma_v4f32: ; @fma_v4f32
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll (1543 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll -march=amdgcn -mcpu=SI -verify-machineinstrs | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll -march=amdgcn -mcpu=tonga -verify-machineinstrs | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function extract_neg_offset_vgpr: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1, %VGPR0
BB#0: derived from LLVM BB %entry
Live Ins: %VGPR0 %SGPR0_SGPR1
%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)](nontemporal)(invariant)
%SGPR3<def> = S_MOV_B32 61440
%SGPR2<def> = S_MOV_B32 -1
%VGPR1<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
%VGPR2<def> = V_MOV_B32_e32 1, %EXEC<imp-use>
%VGPR3<def> = V_MOV_B32_e32 2, %EXEC<imp-use>
%VGPR4<def> = V_MOV_B32_e32 3, %EXEC<imp-use>
%SGPR4_SGPR5<def> = S_MOV_B64 %EXEC
%VCC_LO<def> = V_READFIRSTLANE_B32 %VGPR0, %EXEC<imp-use>
%M0<def> = S_MOV_B32 %VCC_LO
V_CMP_EQ_U32_e32 %M0, %VGPR0, %VCC<imp-def>, %EXEC<imp-use>
%VCC<def> = S_AND_SAVEEXEC_B64 %VCC, %EXEC<imp-def>, %SCC<imp-def>, %EXEC<imp-use>
%M0<def> = S_ADD_I32 %M0, -511, %SCC<imp-def>
%VGPR0<def> = V_MOVRELS_B32_e32 %VGPR0, %M0<imp-use>, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use>
%EXEC<def> = S_XOR_B64 %EXEC, %VCC, %SCC<imp-def>
S_CBRANCH_EXECNZ -7, %EXEC<imp-use>
%EXEC<def> = S_MOV_B64 %SGPR4_SGPR5
S_WAITCNT 127
BUFFER_STORE_DWORD_OFFSET %VGPR0<kill>, %SGPR0_SGPR1_SGPR2_SGPR3, 0, 0, 0, 0, 0, %EXEC<imp-use>; mem:ST4[%out(addrspace=1)]
S_ENDPGM
# End machine code for function extract_neg_offset_vgpr.
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: extract_neg_offset_vgpr
- basic block: BB#0 entry (0x9faba8)
- instruction: %EXEC<def> = S_MOV_B64
First terminator was: S_CBRANCH_EXECNZ -7, %EXEC<imp-use>
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: extract_neg_offset_vgpr
- basic block: BB#0 entry (0x9faba8)
- instruction: S_WAITCNT
First terminator was: S_CBRANCH_EXECNZ -7, %EXEC<imp-use>
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: extract_neg_offset_vgpr
- basic block: BB#0 entry (0x9faba8)
- instruction: BUFFER_STORE_DWORD_OFFSET
First terminator was: S_CBRANCH_EXECNZ -7, %EXEC<imp-use>
LLVM ERROR: Found 3 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll:82:16: error: expected string not found in input
; CHECK-LABEL: {{^}}extract_neg_offset_vgpr:
^
<stdin>:183:33: note: scanning from here
extract_neg_offset_sgpr_loaded: ; @extract_neg_offset_sgpr_loaded
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/lds-output-queue.ll (1561 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/lds-output-queue.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll -march=r600 -mcpu=redwood -verify-machineinstrs | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function local_global_alias: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %entry
CF_ALU 8, 0, 0, 2, 0, 0, 0, 0, 1
CF_TC_EG 6, 0
CF_ALU 9, 0, 0, 2, 0, 0, 0, 6, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
FETCH_CLAUSE 6
%T0_X<def,tied1> = VTX_READ_GLOBAL_32_eg %T0_X<kill,tied0>, 0; mem:LD4[%in(addrspace=1)]
ALU_CLAUSE 8
%T0_X<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 9
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%OQAP<def> = LDS_READ_RET %T0_W<kill>, 0, -1, 1, pred:%PRED_SEL_OFF, 0; mem:LD4[%0(addrspace=3)]
%T0_Y<def> = MOV 1, 0, 0, 0, %OQAP, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %PV_Y<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function local_global_alias.
*** Bad machine code: Illegal physical register for instruction ***
- function: local_global_alias
- basic block: BB#0 entry (0x11629c8)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_Y<kill>
PV_Y is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll:87:16: error: expected string not found in input
; CHECK-LABEL: {{^}}local_global_alias:
^
<stdin>:12:18: note: scanning from here
lds_input_queue: ; @lds_input_queue
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/lds-oqap-crash.ll (1562 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/lds-oqap-crash.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/lds-oqap-crash.ll -march=r600 -mcpu=redwood -verify-machineinstrs | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/lds-oqap-crash.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function lds_crash: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %entry
CF_ALU 4, 0, 0, 2, 0, 0, 0, 115, 1
CF_ALU 120, 0, 0, 2, 0, 0, 0, 14, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
ALU_CLAUSE 4
%T0_X<def> = RECIP_UINT_eg 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = CNDE_INT 0, 0, %PS, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %T0_Y<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %T0_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %PS<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = RECIP_UINT_eg 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%OQAP<def> = LDS_READ_RET %T0_W<kill>, 0, -1, 1, pred:%PRED_SEL_OFF, 0; mem:LD4[%in(addrspace=3)]
%T0_Y<def> = MOV 1, 0, 0, 0, %OQAP, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = CNDE_INT 0, 0, %T0_Z<kill>, 0, 0, -1, %T1_Y<kill>, 0, 0, -1, %T1_Z<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %PV_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_Z, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = CNDE_INT 0, 0, %PS, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %T0_Z<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T0_Y<kill>, 0, 0, 0, -1, %T1_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T1_X, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %T0_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %PS<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %PV_Z<kill>, 0, 0, -1, %T1_X, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T1_X<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
%T1_W<def> = CNDE_INT 0, 0, %T2_W<kill>, 0, 0, -1, %PS<kill>, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = CNDE_INT 0, 0, %T2_X<kill>, 0, 0, -1, %PV_Y<kill>, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T1_W, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 0, pred:%PRED_SEL_OFF, 0, 0
%T4_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T1_W, 0, 0, 0, -1, %T0_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T5_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = CNDE_INT 0, 0, %PV_W<kill>, 0, 0, -1, %T0_X, 0, 0, -1, %PS<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T5_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
%T3_W<def> = CNDE_INT 0, 0, %T4_W<kill>, 0, 0, -1, %PS<kill>, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1171354717, 0
LITERALS 3123612579, 0
%T4_W<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
LITERALS 3, 0
%T0_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T2_W<kill>, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T4_W, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 0, pred:%PRED_SEL_OFF, 0, 0
%T4_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T4_W<kill>, 0, 0, 0, -1, %T0_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T5_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = CNDE_INT 0, 0, %PV_W<kill>, 0, 0, -1, %T0_X, 0, 0, -1, %PS<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T0_X<def> = RECIP_UINT_eg 1, 0, 0, 0, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 4294967295, 0
%T2_W<def> = CNDE_INT 0, 0, %T4_W<kill>, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T2_W, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T4_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Z<def> = CNDE_INT 0, 0, %PS, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %T0_Y<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T4_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T2_W<kill>, 0, 0, 0, -1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %T0_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %PS<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = CNDE_INT 0, 0, %PV_Z<kill>, 0, 0, -1, %T0_Z, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_Z<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T0_X<def> = RECIP_UINT_eg 1, 0, 0, 0, %T1_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 4294967295, 0
%T0_Z<def> = CNDE_INT 0, 0, %T0_W<kill>, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = CNDE_INT 0, 0, %T1_X<kill>, 0, 0, -1, %PV_X<kill>, 0, 0, -1, %PV_Y<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %T1_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PV_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %T1_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Z<def> = CNDE_INT 0, 0, %PS, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %T0_Y<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %KC0_131_Y, 0, 0, 0, 2061, 0, pred:%PRED_SEL_OFF, 0, 0
%T4_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T0_Z<kill>, 0, 0, 0, -1, %T1_X<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %T0_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %PS<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = CNDE_INT 0, 0, %PV_Z<kill>, 0, 0, -1, %T0_W, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T0_X<def> = RECIP_UINT_eg 1, 0, 0, 0, %T3_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 4294967295, 0
%T0_Z<def> = CNDE_INT 0, 0, %T4_W<kill>, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = CNDE_INT 0, 0, %T1_Y<kill>, 0, 0, -1, %PV_X<kill>, 0, 0, -1, %PV_Y<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %T3_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PV_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %T1_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %T3_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Z<def> = CNDE_INT 0, 0, %PS, 0, 0, -1, %PV_W<kill>, 0, 0, -1, %T0_Y<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %T1_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T0_Z<kill>, 0, 0, 0, -1, %T1_X<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %T0_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Y<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %PS<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %PV_Z<kill>, 0, 0, -1, %T0_W, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
ALU_CLAUSE 120
%T0_W<def> = CNDE_INT 0, 0, %T2_W<kill>, 0, 0, -1, %T0_W<kill>, 0, 0, -1, %T1_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %T1_Y<kill>, 0, 0, -1, %T2_Y<kill>, 0, 0, -1, %T1_Z<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MULHI_UINT_eg 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %T3_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %T3_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SETGE_UINT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %T0_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %PV_W<kill>, 0, 0, -1, %T0_X, 0, 0, -1, %PS<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
%T0_X<def> = CNDE_INT 0, 0, %T0_W<kill>, 0, 0, -1, %PS<kill>, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function lds_crash.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = CNDE_INT
- operand 3: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULHI_UINT_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Y<def> = ADD_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = SUB_INT
- operand 12: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_X<def> = MULHI_UINT_eg
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_X<def> = MULHI_UINT_eg
- operand 12: %PV_Y
PV_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 3: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = SETGE_UINT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULHI_UINT_eg
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Y<def> = ADD_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = SUB_INT
- operand 12: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 3: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = CNDE_INT
- operand 7: %PV_Y<kill>
PV_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = CNDE_INT
- operand 11: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = MULHI_UINT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = MULHI_UINT_eg
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = SETGE_UINT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = CNDE_INT
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = CNDE_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T3_W<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = MULHI_UINT_eg
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T4_W<def> = LSHR_eg
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = MULHI_UINT_eg
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = SETGE_UINT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = CNDE_INT
- operand 11: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = MULHI_UINT_eg
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Z<def> = CNDE_INT
- operand 3: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Z<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T4_W<def> = SETGE_UINT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULHI_UINT_eg
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_X<def> = ADD_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = SUB_INT
- operand 12: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = CNDE_INT
- operand 3: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 11: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = CNDE_INT
- operand 11: %PV_Y<kill>
PV_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = MULHI_UINT_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = MULHI_UINT_eg
- operand 12: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_X<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Z<def> = CNDE_INT
- operand 3: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Z<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_W<def> = SETGE_UINT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULHI_UINT_eg
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_X<def> = ADD_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = SUB_INT
- operand 12: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 3: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = CNDE_INT
- operand 11: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = CNDE_INT
- operand 11: %PV_Y<kill>
PV_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = MULHI_UINT_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_W<def> = MULHI_UINT_eg
- operand 12: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_X<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Z<def> = CNDE_INT
- operand 3: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Z<def> = CNDE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = SETGE_UINT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Z<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULHI_UINT_eg
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T2_Y<def> = ADD_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_Z<def> = SUB_INT
- operand 12: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 3: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = MULHI_UINT_eg
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = MULHI_UINT_eg
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_Y<def> = MULLO_INT_eg
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = SUB_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = SETGE_UINT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = AND_INT
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = CNDE_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_crash
- basic block: BB#0 entry (0x71d6b8)
- instruction: %T0_X<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 109 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.abs.ll (1568 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.abs.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function s_abs_i32: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 3, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MAX_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %KC0_130_Z, 0, 0, 0, 2058, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function s_abs_i32.
*** Bad machine code: Illegal physical register for instruction ***
- function: s_abs_i32
- basic block: BB#0 (0xc5cfe8)
- instruction: %T0_X<def> = MAX_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll (1572 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function bfm_imm_imm: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 4, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 456, 0
LITERALS 456, 0
%T0_X<def> = BFM_INT_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 123, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 123, 2
# End machine code for function bfm_imm_imm.
*** Bad machine code: Illegal physical register for instruction ***
- function: bfm_imm_imm
- basic block: BB#0 (0x2683da8)
- instruction: %T0_X<def> = BFM_INT_eg
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: bfm_imm_imm
- basic block: BB#0 (0x2683da8)
- instruction: %T1_X<def> = LSHR_eg
- operand 12: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
LLVM ERROR: Found 2 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll:34:15: error: expected string not found in input
; FUNC-LABEL: {{^}}bfm_imm_imm:
^
<stdin>:59:14: note: scanning from here
bfm_imm_arg: ; @bfm_imm_arg
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll (1573 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function clamp_0_1_f32: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 3, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_W<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MOV 1, 0, 0, 1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function clamp_0_1_f32.
*** Bad machine code: Illegal physical register for instruction ***
- function: clamp_0_1_f32
- basic block: BB#0 (0x22148c8)
- instruction: %T0_X<def> = MOV
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll (1575 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood -show-mc-encoding -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function v_bfe_print_arg: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 8, 0, 0, 2, 0, 0, 0, 0, 1
CF_TC_EG 6, 0
CF_ALU 9, 0, 0, 2, 0, 0, 0, 4, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
FETCH_CLAUSE 6
%T0_X<def,tied1> = VTX_READ_GLOBAL_32_eg %T0_X<kill,tied0>, 0; mem:LD4[%src0(addrspace=1)]
ALU_CLAUSE 8
%T0_X<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 9
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 8, 0
LITERALS 8, 0
%T0_X<def> = BFE_INT_eg 0, 0, %T0_X<kill>, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function v_bfe_print_arg.
*** Bad machine code: Illegal physical register for instruction ***
- function: v_bfe_print_arg
- basic block: BB#0 (0x23e3258)
- instruction: %T0_X<def> = BFE_INT_eg
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll:44:15: error: expected string not found in input
; FUNC-LABEL: {{^}}v_bfe_print_arg:
^
<stdin>:83:22: note: scanning from here
bfe_i32_imm_arg_arg: ; @bfe_i32_imm_arg_arg
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll (1579 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function bfe_u32_arg_0_width_reg_offset: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 2, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 0, 2
# End machine code for function bfe_u32_arg_0_width_reg_offset.
*** Bad machine code: Illegal physical register for instruction ***
- function: bfe_u32_arg_0_width_reg_offset
- basic block: BB#0 (0xf9bbc8)
- instruction: %T1_X<def> = LSHR_eg
- operand 12: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll:43:15: error: expected string not found in input
; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_reg_offset:
^
<stdin>:83:22: note: scanning from here
bfe_u32_imm_arg_arg: ; @bfe_u32_imm_arg_arg
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll (1585 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cayman -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=CM -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=R600 -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function test_imad24: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 3, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_X<def> = MULLO_INT_eg 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function test_imad24.
*** Bad machine code: Illegal physical register for instruction ***
- function: test_imad24
- basic block: BB#0 (0x106f478)
- instruction: %T0_X<def> = ADD_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll (1598 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function rsq_f32_constant_4.0: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 2, 1
RAT_WRITE_CACHELESS_32_eg %T1_X<kill>, %T0_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T1_X<def> = RECIPSQRT_IEEE_eg 1, 0, 0, 0, %ALU_LITERAL_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1082130432, 0
LITERALS 2, 1082130432
# End machine code for function rsq_f32_constant_4.0.
*** Bad machine code: Illegal physical register for instruction ***
- function: rsq_f32_constant_4.0
- basic block: BB#0 (0xb66aa8)
- instruction: %T1_X<def> = RECIPSQRT_IEEE_eg
- operand 5: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll:17:15: error: expected string not found in input
; FUNC-LABEL: {{^}}rsq_f32_constant_4.0
^
<stdin>:12:10: note: scanning from here
rsq_f32: ; @rsq_f32
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll (1603 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cayman -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function commute_umad24: Post SSA, not tracking liveness
Function Live Ins: %T0_X
BB#0: derived from LLVM BB %0
Live Ins: %T0_X
CF_ALU 10, 0, 0, 2, 0, 0, 0, 5, 1
CF_TC_EG 6, 1
CF_ALU 16, 0, 0, 0, 0, 0, 0, 1, 1
RAT_STORE_DWORD32 %T0_X<kill>, %T1_X<kill>; mem:ST4[%out.gep(addrspace=1)]
CF_END_CM
PAD
FETCH_CLAUSE 6
%T2_X<def,tied1> = VTX_READ_GLOBAL_32_cm %T2_X<kill,tied0>, 0; mem:LD4[%src0.gep(addrspace=1)]
%T0_X<def,tied1> = VTX_READ_GLOBAL_32_cm %T0_X<kill,tied0>, 4; mem:LD4[%src2.gep(addrspace=1)]
ALU_CLAUSE 10
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_X, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
%T2_X<def> = MOV 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 16
%T0_X<def> = MULADD_UINT24_eg 0, 0, %T2_X<kill>, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, %T0_X<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 4, 0
LITERALS 4, 0
# End machine code for function commute_umad24.
*** Bad machine code: Illegal physical register for instruction ***
- function: commute_umad24
- basic block: BB#0 (0x238b098)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll:21:15: error: expected string not found in input
; FUNC-LABEL: {{^}}commute_umad24:
^
<stdin>:12:14: note: scanning from here
test_umad24: ; @test_umad24
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/load-i1.ll (1647 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/load-i1.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/load-i1.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/load-i1.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/load-i1.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/load-i1.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/load-i1.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/load-i1.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function global_copy_i1_to_i1: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 8, 0, 0, 2, 0, 0, 0, 0, 1
CF_TC_EG 6, 0
CF_ALU 9, 0, 0, 2, 0, 0, 0, 11, 1
RAT_MSKOR %T1_XYZW, %T0_X<kill>; mem:ST1[%out(addrspace=1)]
CF_END_EG
PAD
FETCH_CLAUSE 6
%T0_X<def> = VTX_READ_GLOBAL_8_eg %T0_X<kill>, 0; mem:LD1[%in(addrspace=1)]
ALU_CLAUSE 8
%T0_X<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 9
%T0_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 3, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 3, 0
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
LITERALS 3, 0
%T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 255, 0
LITERALS 255, 0
%T1_Y<def> = MOV 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function global_copy_i1_to_i1.
*** Bad machine code: Illegal physical register for instruction ***
- function: global_copy_i1_to_i1
- basic block: BB#0 (0x223ee08)
- instruction: %T0_W<def> = LSHL_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: global_copy_i1_to_i1
- basic block: BB#0 (0x223ee08)
- instruction: %T1_X<def> = LSHL_eg
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: global_copy_i1_to_i1
- basic block: BB#0 (0x223ee08)
- instruction: %T1_W<def> = LSHL_eg
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 3 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/local-atomics.ll (1662 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/local-atomics.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/local-atomics.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function lds_atomic_xchg_ret_i32: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 5, 1
RAT_WRITE_CACHELESS_32_eg %T1_X<kill>, %T0_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 4, 0
%T1_W<def> = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 2, 4
%OQAP<def> = LDS_WRXCHG_RET %T1_W<kill>, 0, -1, %T0_W<kill>, 0, -1, 1, pred:%PRED_SEL_OFF, 0; mem:Volatile LDST4[%ptr(addrspace=3)]
%T1_X<def> = MOV 1, 0, 0, 0, %OQAP, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
# End machine code for function lds_atomic_xchg_ret_i32.
*** Bad machine code: Illegal physical register for instruction ***
- function: lds_atomic_xchg_ret_i32
- basic block: BB#0 (0x25c30d8)
- instruction: %T0_W<def> = MOV
- operand 5: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/saddo.ll (1715 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/saddo.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/saddo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/saddo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/saddo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/saddo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/saddo.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function saddo_i64_zext: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 26, 1
RAT_WRITE_CACHELESS_32_eg %T2_X<kill>, %T3_X<kill>, 0
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
ALU_CLAUSE 4
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %KC0_131_Z, 0, 0, 0, 2062, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = ADDC_UINT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %KC0_131_Z, 0, 0, 0, 2062, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T1_W<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T2_W<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
%T1_Z<def> = CNDE_INT 0, 0, %KC0_131_X, 0, 0, 2060, %ONE_INT, 0, 0, -1, %PS<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %T0_W, 0, 0, -1, %ONE_INT, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = CNDE_INT 0, 0, %KC0_131_Z, 0, 0, 2062, %ONE_INT, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 1
%T0_Z<def> = AND_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %PV_Z<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADDC_UINT 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 4, 0
LITERALS 4, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T2_X<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T3_W<kill>, 0, 0, 0, -1, %T1_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 2, 0
%T3_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function saddo_i64_zext.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T0_W<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = SETGT_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_Z<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = CNDE_INT
- operand 11: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T0_Z<def> = AND_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = AND_INT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = SETNE_INT
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = SETNE_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = SETE_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = SETE_INT
- operand 12: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = AND_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_W<def> = AND_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = AND_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = ADDC_UINT
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T2_W<def> = ADDC_UINT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: saddo_i64_zext
- basic block: BB#0 (0x2073c78)
- instruction: %T1_X<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 19 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll (1718 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %T1_XYZW
BB#0: derived from LLVM BB %main_body
Live Ins: %T1_XYZW
CF_CALL_FS_EG
CF_ALU_PUSH_BEFORE 8, 0, 0, 0, 0, 0, 0, 10, 1
CF_JUMP_EG 4, 1
CF_ALU_POP_AFTER 19, 0, 0, 0, 0, 0, 0, 10, 1
CF_ALU 30, 0, 0, 0, 0, 0, 0, 11, 1
EG_ExportSwz %T2_XYZW, 0, 0, 0, 1, 2, 3, 84, 1
CF_END_CM
PAD
ALU_CLAUSE 8
%T0_W<def> = SGE 0, 0, 1, 0, 0, 0, %T1_X, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1113849856, 0
LITERALS 1113849856, 0
%T0_Z<def> = SETE_DX10 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = CNDGE_eg 0, 0, %T1_Y, 0, 0, -1, %ZERO, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
%T0_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PV_Z<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = CNDGE_eg 0, 0, %T1_X, 0, 0, -1, %ZERO, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1, 0
%T0_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 4294967295, 1
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 19
%T1_Z<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%T1_Y<def> = SETE_INT 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MOV 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1065353216, 0
LITERALS 1065353216, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 0, 1, 0, 0, 0, 0, %PV_Y, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_ONE, 1065353216, 0, %PREDICATE_BIT<imp-use>, %T0_Z<imp-use,undef>
LITERALS 1065353216, 0
%T0_W<def> = MOV 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_ONE, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
%T1_Y<def> = MOV 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 30
%T1_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %T1_Z<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 0, 1, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = CNDE_INT 0, 0, %T0_Y, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, %ZERO, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 1065353216, 0, %PREDICATE_BIT<imp-use>, %T1_Y<imp-use,undef>
%T0_Z<def> = CNDE_INT 0, 0, %T0_Y<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 1065353216, 0, %PREDICATE_BIT<imp-use>, %T0_Z<imp-use,undef>
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
LITERALS 1065353216, 0
%T1_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1065353216, 0
LITERALS 1065353216, 0
%T2_W<def> = MOV 1, 0, 0, 1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Z<def> = MOV 1, 0, 0, 1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Y<def> = MOV 1, 0, 0, 1, %T1_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = MOV 1, 0, 0, 1, %T0_Z<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
# End machine code for function main.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T0_Z<def> = SETE_DX10
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T0_W<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T0_W<def> = AND_INT
- operand 12: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T1_Z<def> = MOV
- operand 5: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T0_W<def> = SETE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T0_Z<def> = MOV
- operand 5: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_Y
PV_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T0_W<def> = MOV
- operand 5: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xc0a0e8)
- instruction: %T2_W<def> = MOV
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 14 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested.ll (1719 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function main: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %main_body
CF_ALU 20, 1, 0, 2, 0, 0, 0, 18, 1
WHILE_LOOP_EG 17
CF_ALU_PUSH_BEFORE 39, 0, 0, 0, 0, 0, 0, 10, 1
CF_JUMP_EG 12, 1
WHILE_LOOP_EG 11
CF_PUSH_EG 6, 1
CF_ALU 50, 0, 0, 0, 0, 0, 0, 11, 1
CF_JUMP_EG 10, 1
LOOP_BREAK_EG 10
POP_EG 10, 1
END_LOOP_EG 5
CF_ALU_POP_AFTER 62, 0, 0, 0, 0, 0, 0, 1, 1
CF_ALU_PUSH_BEFORE 64, 0, 0, 0, 0, 0, 0, 1, 1
CF_JUMP_EG 16, 1
LOOP_BREAK_EG 16
POP_EG 16, 1
END_LOOP_EG 2
CF_ALU 66, 0, 0, 0, 0, 0, 0, 5, 1
EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1
CF_END_CM
ALU_CLAUSE 20
%T0_W<def> = TRUNC 1, 0, 0, 0, %KC0_128_W, 0, 0, 0, 18435, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = FLT_TO_INT_eg 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ASHR_eg 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 31, 0
LITERALS 31, 0
%T0_W<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 30, 0
LITERALS 30, 0
%T1_Z<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T1_W, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%T0_X<def> = MOV 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1, 0
%T0_Z<def> = ASHR_eg 0, 0, 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, %ALU_LITERAL_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T2_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %ALU_LITERAL_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -4, 0
LITERALS 1, 2
LITERALS 4294967292, 0
%T1_X<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = MOV 1, 0, 0, 0, %KC0_128_X, 0, 0, 0, 18432, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %KC0_128_Y, 0, 0, 0, 18433, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = MOV 1, 0, 0, 0, %KC0_128_Z, 0, 0, 0, 18434, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 39
%T3_Y<def> = MOV 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = MOV 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = MOV 1, 0, 0, 0, %T1_Z<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_Y<def> = MOV 1, 0, 0, 0, %T1_Y<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = SETGE_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %T0_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Z<def> = MOV 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_X<def> = MOV 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = SETE_INT 0, 0, 1, 0, 0, 0, %T1_Z<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %T2_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = MOV 1, 0, 0, 0, %T2_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_Y, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 50
%T1_Y<def> = MOV 1, 0, 0, 0, %T1_Z<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETGE_INT 0, 0, 1, 0, 0, 0, %T2_W, 0, 0, 0, -1, %T1_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 2
%T3_Y<def> = MOV 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_Z<def> = SETE_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = MOV 1, 0, 0, 0, %T3_X<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 0, 1, 0, 0, 0, 0, %PV_Z, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_Y<def> = MOV 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_ONE, 0, 0, %PREDICATE_BIT<imp-use>, %T3_Y<imp-use,undef>
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T2_W<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_ONE, 0, 2, %PREDICATE_BIT<imp-use>, %T2_W<imp-use,undef>
%T3_X<def> = MOV 1, 0, 0, 0, %T1_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = BFE_INT_eg 0, 0, %T3_Y<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ONE_INT, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 2
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 62
%T3_Y<def> = MOV 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 64
%T2_W<def> = BFE_INT_eg 0, 0, %T3_Y<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ONE_INT, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 66
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1065353216, 0
LITERALS 1065353216, 0
%T0_W<def> = MOV 1, 0, 0, 1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MOV 1, 0, 0, 1, %T2_Z<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Y<def> = MOV 1, 0, 0, 1, %T2_X<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MOV 1, 0, 0, 1, %T2_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
# End machine code for function main.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T1_W<def> = FLT_TO_INT_eg
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T0_W<def> = ASHR_eg
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T0_W<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T1_Z<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T0_X<def> = MOV
- operand 5: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T0_Z<def> = ASHR_eg
- operand 7: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T0_Z<def> = ASHR_eg
- operand 12: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T2_W<def> = AND_INT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T2_W<def> = AND_INT
- operand 12: %ALU_LITERAL_Z
ALU_LITERAL_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T1_X<def> = SUB_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T3_X<def> = MOV
- operand 5: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_Y
PV_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T3_Z<def> = SETE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x768f28)
- instruction: %T0_W<def> = MOV
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 21 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/schedule-fs-loop.ll (1721 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/schedule-fs-loop.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function main: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %main_body
CF_ALU 10, 1, 0, 2, 0, 0, 0, 9, 1
WHILE_LOOP_EG 7
CF_ALU_PUSH_BEFORE 20, 0, 0, 0, 0, 0, 0, 12, 1
CF_JUMP_EG 6, 1
LOOP_BREAK_EG 6
POP_EG 6, 1
END_LOOP_EG 2
CF_ALU 33, 0, 0, 0, 0, 0, 0, 5, 1
EG_ExportSwz %T2_XYZW, 0, 0, 0, 1, 2, 3, 84, 1
CF_END_CM
ALU_CLAUSE 10
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%T0_X<def> = MOV 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1, 0
%T1_W<def> = TRUNC 1, 0, 0, 0, %KC0_128_W, 0, 0, 0, 18435, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 1, 0
%T1_X<def> = FLT_TO_INT_eg 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_Y<def> = MOV 1, 0, 0, 0, %KC0_128_X, 0, 0, 0, 18432, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %KC0_128_Y, 0, 0, 0, 18433, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = MOV 1, 0, 0, 0, %KC0_128_Z, 0, 0, 0, 18434, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 20
%T0_Y<def> = MOV 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETGE_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %T1_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = MOV 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = MOV 1, 0, 0, 0, %T1_Z<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 2
%T1_Z<def> = SETE_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = MOV 1, 0, 0, 0, %T2_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 0, 1, 0, 0, 0, 0, %PV_Z, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = MOV 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_ONE, 0, 0, %PREDICATE_BIT<imp-use>, %T2_X<imp-use,undef>
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_X<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_ONE, 0, 0, %PREDICATE_BIT<imp-use>, %T0_X<imp-use,undef>
%T2_Y<def> = MOV 1, 0, 0, 0, %T1_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 2
%T2_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %T2_X<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 33
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1065353216, 0
LITERALS 1065353216, 0
%T2_W<def> = MOV 1, 0, 0, 1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Z<def> = MOV 1, 0, 0, 1, %T0_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_Y<def> = MOV 1, 0, 0, 1, %T1_Y<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_X<def> = MOV 1, 0, 0, 1, %T1_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
# End machine code for function main.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %T0_X<def> = MOV
- operand 5: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %T1_X<def> = FLT_TO_INT_eg
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %T1_Z<def> = SETE_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %PREDICATE_BIT<def> = PRED_SETE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %PREDICATE_BIT<def> = PRED_SETE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0xf811a8)
- instruction: %T2_W<def> = MOV
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 8 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/schedule-if-2.ll (1723 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/schedule-if-2.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function main: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %main_body
CF_ALU_PUSH_BEFORE 10, 0, 0, 2, 0, 0, 0, 4, 1
CF_JUMP_EG 6, 1
CF_ALU_PUSH_BEFORE 15, 0, 0, 2, 0, 0, 0, 5, 1
CF_JUMP_EG 5, 1
CF_ALU_POP_AFTER 21, 0, 0, 2, 0, 0, 0, 4, 1
POP_EG 6, 1
CF_ALU 26, 0, 0, 0, 0, 0, 0, 23, 1
EG_ExportSwz %T1_XYZW, 0, 0, 0, 1, 2, 3, 84, 1
CF_END_CM
PAD
ALU_CLAUSE 10
%T0_Y<def> = ADD 0, 0, 1, 0, 0, 0, %KC0_130_X, 0, 0, 0, 2056, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1148846080, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1, 0
%T0_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %KC0_129_X, 0, 0, 0, 2052, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 1148846080, 1
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 15
%T1_Z<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%T1_Y<def> = MOV 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = MOV 1, 0, 0, 0, %T1_Z, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %KC0_129_X, 0, 0, 0, 2052, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 21
%T0_W<def> = SGE 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SETE_DX10 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_Y<def> = ADD 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %KC0_128_X, 1, 0, 0, 2048, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = CNDE_INT 0, 0, %PV_W<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ONE_INT, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = INT_TO_FLT_eg 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 26
%T0_W<def> = MOV 1, 0, 0, 0, %T1_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %T1_Z, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 0, 1, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SETNE_DX10 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %T0_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
%T0_W<def> = OR_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
%T0_W<def> = CNDE_INT 0, 0, %T0_W<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 1065353216, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
LITERALS 1065353216, 0
%T0_W<def> = TRUNC 1, 0, 0, 0, %T0_W<kill>, 1, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
%T1_Y<def> = SGE 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T1_Y<imp-use,undef>
%T0_Z<def> = FLT_TO_INT_eg 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_Z<imp-use,undef>
%T0_W<def> = SGT 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %T0_Y, 0, 0, 1, -1, 1, pred:%PRED_SEL_ZERO, 2139095040, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
LITERALS 2139095040, 0
%T2_Y<def> = SETE_DX10 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T2_Y<imp-use,undef>
%T0_Z<def> = CNDE_INT 0, 0, %T0_Z<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ONE_INT, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_Z<imp-use,undef>
%T0_W<def> = CNDE_eg 0, 0, %T1_Y<kill>, 0, 0, -1, %ONE, 0, 0, -1, %T0_Y, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
%T3_Y<def> = SGT 0, 0, 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T3_Y<imp-use,undef>
%T1_Z<def> = INT_TO_FLT_eg 1, 0, 0, 0, %T0_Z<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T1_Z<imp-use,undef>
%T1_W<def> = CNDE_INT 0, 0, %T2_Y<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ONE_INT, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T1_W<imp-use,undef>
%T1_Y<def> = INT_TO_FLT_eg 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T1_Y<imp-use,undef>
%T0_W<def> = CNDE_eg 0, 0, %T3_Y<kill>, 0, 0, -1, %T0_W<kill>, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, -1082130432, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
LITERALS 3212836864, 0
%T1_X<def> = MOV 1, 0, 0, 0, %T0_Y<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T1_X<imp-use,undef>
%T0_W<def> = MULADD_IEEE_eg 0, 0, %T0_W<kill>, 0, 0, -1, %HALF, 0, 0, -1, %HALF, 0, 0, -1, 1, pred:%PRED_SEL_ZERO, 0, 0, %PREDICATE_BIT<imp-use>, %T0_W<imp-use,undef>
%T1_W<def> = MOV 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
# End machine code for function main.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %T1_Z<def> = MOV
- operand 5: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %T1_Y<def> = MOV
- operand 5: %PV_Z
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %T0_W<def> = SETE_DX10
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %T0_W<def> = CNDE_INT
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %T1_X<def> = INT_TO_FLT_eg
- operand 5: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x19ea0b8)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 11 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/schedule-if.ll (1725 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/schedule-if.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/schedule-if.ll -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function main: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %main_body
CF_ALU_PUSH_BEFORE 8, 0, 0, 2, 0, 0, 0, 7, 1
CF_JUMP_EG 6, 1
CF_ALU_PUSH_BEFORE 16, 0, 0, 2, 0, 0, 0, 5, 1
CF_JUMP_EG 5, 1
CF_ALU_POP_AFTER 22, 0, 0, 2, 0, 0, 0, 2, 1
POP_EG 6, 1
EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 4, 3, 84, 1
CF_END_CM
ALU_CLAUSE 8
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1065353216, 0
LITERALS 1065353216, 0
%T0_Y<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%T0_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1148846080, 0
%T1_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %KC0_129_X, 0, 0, 0, 2052, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 1148846080, 0
%PREDICATE_BIT<def> = PRED_SETE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 16
%T0_W<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 0, 0
%T0_Y<def> = MOV 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = MOV 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %KC0_129_X, 0, 0, 0, 2052, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%PREDICATE_BIT<def> = PRED_SETNE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
ALU_CLAUSE 22
%T0_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 1065353216, 0
%T0_Y<def> = ADD 0, 0, 1, 0, 0, 0, %KC0_128_X, 1, 0, 0, 2048, %ALU_LITERAL_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 1148846080, 0
LITERALS 1065353216, 1148846080
# End machine code for function main.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x1c93d18)
- instruction: %PREDICATE_BIT<def> = PRED_SETE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x1c93d18)
- instruction: %PREDICATE_BIT<def> = PRED_SETE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x1c93d18)
- instruction: %T0_Y<def> = MOV
- operand 5: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x1c93d18)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 0: %PREDICATE_BIT<def>
PREDICATE_BIT is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x1c93d18)
- instruction: %PREDICATE_BIT<def> = PRED_SETNE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: main
- basic block: BB#0 main_body (0x1c93d18)
- instruction: %T0_Y<def> = ADD
- operand 12: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
LLVM ERROR: Found 6 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/selectcc.ll (1739 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/selectcc.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -verify-machineinstrs -march=r600 -mcpu=redwood < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/selectcc.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/selectcc.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -verify-machineinstrs -march=amdgcn -mcpu=SI < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/selectcc.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/selectcc.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/selectcc.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/selectcc.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function selectcc_i64: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %entry
CF_ALU 4, 0, 0, 2, 0, 0, 0, 10, 1
RAT_WRITE_CACHELESS_32_eg %T2_X<kill>, %T3_X<kill>, 0
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
ALU_CLAUSE 4
%T0_W<def> = XOR_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = XOR_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %KC0_131_Z, 0, 0, 0, 2062, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = OR_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = CNDE_INT 0, 0, %PV_W, 0, 0, -1, %KC0_131_W, 0, 0, 2063, %KC0_132_Y, 0, 0, 2065, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
%T2_X<def> = CNDE_INT 0, 0, %T0_W<kill>, 0, 0, -1, %KC0_132_X, 0, 0, 2064, %KC0_132_Z, 0, 0, 2066, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 4, 0
LITERALS 4, 0
%T3_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function selectcc_i64.
*** Bad machine code: Illegal physical register for instruction ***
- function: selectcc_i64
- basic block: BB#0 entry (0x1317158)
- instruction: %T0_W<def> = OR_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: selectcc_i64
- basic block: BB#0 entry (0x1317158)
- instruction: %T0_X<def> = CNDE_INT
- operand 3: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: selectcc_i64
- basic block: BB#0 entry (0x1317158)
- instruction: %T3_X<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 3 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/sext-eliminate.ll (1746 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/sext-eliminate.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-eliminate.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-eliminate.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function sext_in_reg_i1_i32_add: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 3, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = SUB_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function sext_in_reg_i1_i32_add.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_in_reg_i1_i32_add
- basic block: BB#0 (0x1f506d8)
- instruction: %T0_X<def> = SUB_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/setcc-opt.ll (1747 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/setcc-opt.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/setcc-opt.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/setcc-opt.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/setcc-opt.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/setcc-opt.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/setcc-opt.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/setcc-opt.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function sext_bool_icmp_eq_0: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 12, 1
RAT_MSKOR %T1_XYZW, %T0_X<kill>; mem:ST1[%out(addrspace=1)]
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 3, 0
%T1_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 3, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
LITERALS 3, 0
%T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %PS<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 255, 0
LITERALS 255, 0
%T1_Y<def> = MOV 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_Z<def> = MOV 1, 0, 0, 0, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function sext_bool_icmp_eq_0.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_bool_icmp_eq_0
- basic block: BB#0 (0x222f0a8)
- instruction: %T1_W<def> = AND_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_bool_icmp_eq_0
- basic block: BB#0 (0x222f0a8)
- instruction: %T0_W<def> = LSHL_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_bool_icmp_eq_0
- basic block: BB#0 (0x222f0a8)
- instruction: %T1_X<def> = LSHL_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_bool_icmp_eq_0
- basic block: BB#0 (0x222f0a8)
- instruction: %T1_X<def> = LSHL_eg
- operand 12: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_bool_icmp_eq_0
- basic block: BB#0 (0x222f0a8)
- instruction: %T1_W<def> = LSHL_eg
- operand 12: %PS<kill>
PS is not a R600_Reg32 register.
LLVM ERROR: Found 5 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/sext-in-reg.ll (1755 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/sext-in-reg.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function sext_in_reg_i8_to_i32: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 3, 1
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
PAD
ALU_CLAUSE 4
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = BFE_INT_eg 0, 0, %PV_W<kill>, 0, 0, -1, %ZERO, 0, 0, -1, %ALU_LITERAL_X, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 8, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 8, 2
# End machine code for function sext_in_reg_i8_to_i32.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_in_reg_i8_to_i32
- basic block: BB#0 (0x14e46e8)
- instruction: %T0_X<def> = BFE_INT_eg
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: sext_in_reg_i8_to_i32
- basic block: BB#0 (0x14e46e8)
- instruction: %T1_X<def> = LSHR_eg
- operand 12: %ALU_LITERAL_Y
ALU_LITERAL_Y is not a R600_Reg32 register.
LLVM ERROR: Found 2 machine code errors.
/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll:24:15: error: expected string not found in input
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32:
^
<stdin>:12:21: note: scanning from here
sext_in_reg_i1_i32: ; @sext_in_reg_i1_i32
^
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/ssubo.ll (1778 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/ssubo.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ssubo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ssubo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ssubo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ssubo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/ssubo.ll
--
Exit Code: 1
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function ssubo_i64_zext: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 26, 1
RAT_WRITE_CACHELESS_32_eg %T2_X<kill>, %T3_X<kill>, 0
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
ALU_CLAUSE 4
%T0_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %KC0_131_Z, 0, 0, 0, 2062, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SUBB_UINT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %KC0_131_Z, 0, 0, 0, 2062, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T1_W<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, -1, 0
%T2_W<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -1, 0
LITERALS 4294967295, 0
%T1_Z<def> = CNDE_INT 0, 0, %KC0_131_X, 0, 0, 2060, %ONE_INT, 0, 0, -1, %PS<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %T0_W, 0, 0, -1, %ONE_INT, 0, 0, -1, %PV_W<kill>, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = CNDE_INT 0, 0, %KC0_131_Z, 0, 0, 2062, %ONE_INT, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 1
%T0_Z<def> = AND_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_Z<kill>, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SETNE_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %PV_Z<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PS<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADDC_UINT 0, 0, 1, 0, 0, 0, %PS, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 4, 0
LITERALS 4, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T2_X<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T3_W<kill>, 0, 0, 0, -1, %T1_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 2, 0
%T3_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function ssubo_i64_zext.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T0_W<def> = SUB_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = SETGT_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_Z<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = CNDE_INT
- operand 11: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T0_Z<def> = AND_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = AND_INT
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = AND_INT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = SETNE_INT
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = SETNE_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = SETNE_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = SETNE_INT
- operand 12: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = AND_INT
- operand 7: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_W<def> = AND_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = AND_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = ADDC_UINT
- operand 7: %PS
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T2_W<def> = ADDC_UINT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: ssubo_i64_zext
- basic block: BB#0 (0xc55c78)
- instruction: %T1_X<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 19 machine code errors.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/uaddo.ll (1800 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/uaddo.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/uaddo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/uaddo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/uaddo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/uaddo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/uaddo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/uaddo.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function uaddo_i64_zext: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 17, 1
RAT_WRITE_CACHELESS_32_eg %T2_X<kill>, %T3_X<kill>, 0
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
ALU_CLAUSE 4
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %KC0_131_Z, 0, 0, 0, 2062, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = ADDC_UINT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = SETGT_UINT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = SETGT_UINT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %T2_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %PV_W<kill>, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, %PS<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = ADDC_UINT 0, 0, 1, 0, 0, 0, %T2_W, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 4, 0
LITERALS 4, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T2_X<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T2_W<kill>, 0, 0, 0, -1, %T1_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 2, 0
%T3_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function uaddo_i64_zext.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T0_W<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T0_Z<def> = SETGT_UINT
- operand 12: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T1_W<def> = SETE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T1_W<def> = CNDE_INT
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T1_W<def> = CNDE_INT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T3_W<def> = AND_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T3_W<def> = ADDC_UINT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: uaddo_i64_zext
- basic block: BB#0 (0x1a09c68)
- instruction: %T1_X<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 10 machine code errors.
FileCheck error: '-' is empty.
--
********************
FAIL: LLVM :: CodeGen/AMDGPU/usubo.ll (1812 of 15390)
******************** TEST 'LLVM :: CodeGen/AMDGPU/usubo.ll' FAILED ********************
Script:
--
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=SI -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/usubo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/usubo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/usubo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/usubo.ll
/home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=cypress -verify-machineinstrs< /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/usubo.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/usubo.ll
--
Exit Code: 2
Command Output (stderr):
--
# After Live DEBUG_VALUE analysis
# Machine code for function usubo_i64_zext: Post SSA, not tracking liveness
BB#0: derived from LLVM BB %0
CF_ALU 4, 0, 0, 2, 0, 0, 0, 17, 1
RAT_WRITE_CACHELESS_32_eg %T2_X<kill>, %T3_X<kill>, 0
RAT_WRITE_CACHELESS_32_eg %T0_X<kill>, %T1_X<kill>, 1
CF_END_EG
ALU_CLAUSE 4
%T0_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %KC0_131_Z, 0, 0, 0, 2062, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SUBB_UINT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 0, pred:%PRED_SEL_OFF, 0, 0
%T2_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %KC0_130_W, 0, 0, 0, 2059, %KC0_131_Y, 0, 0, 0, 2061, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_Z<def> = SETGT_UINT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 0, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = SETE_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %KC0_131_X, 0, 0, 0, 2060, 0, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = SETGT_UINT 0, 0, 1, 0, 0, 0, %T2_W, 0, 0, 0, -1, %KC0_130_W, 0, 0, 0, 2059, 1, pred:%PRED_SEL_OFF, 0, 0
%T1_W<def> = CNDE_INT 0, 0, %PV_W<kill>, 0, 0, -1, %PV_Z<kill>, 0, 0, -1, %PS<kill>, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = AND_INT 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T3_W<def> = ADDC_UINT 0, 0, 1, 0, 0, 0, %T2_W, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
%T0_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %PV_W<kill>, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0
%T0_W<def> = ADD_INT 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 4, 0
LITERALS 4, 0
%T1_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %PV_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0
%T2_X<def> = SUB_INT 0, 0, 1, 0, 0, 0, %T2_W<kill>, 0, 0, 0, -1, %T1_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0
LITERALS 2, 0
%T3_X<def> = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0
LITERALS 2, 0
# End machine code for function usubo_i64_zext.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T0_W<def> = SUB_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T0_Z<def> = SETGT_UINT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T1_W<def> = SETE_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T1_W<def> = CNDE_INT
- operand 3: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T1_W<def> = CNDE_INT
- operand 7: %PV_Z<kill>
PV_Z is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T1_W<def> = CNDE_INT
- operand 11: %PS<kill>
PS is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T3_W<def> = AND_INT
- operand 7: %PV_W
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T3_W<def> = ADDC_UINT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T0_X<def> = ADD_INT
- operand 12: %PV_W<kill>
PV_W is not a R600_Reg32 register.
*** Bad machine code: Illegal physical register for instruction ***
- function: usubo_i64_zext
- basic block: BB#0 (0x1d99c98)
- instruction: %T1_X<def> = LSHR_eg
- operand 7: %PV_W<kill>
PV_W is not a R600_Reg32 register.
LLVM ERROR: Found 10 machine code errors.
FileCheck error: '-' is empty.
--
********************
Testing Time: 92.55s
********************
Failing Tests (29):
LLVM :: CodeGen/AMDGPU/basic-loop.ll
LLVM :: CodeGen/AMDGPU/ctpop.ll
LLVM :: CodeGen/AMDGPU/fma.ll
LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll
LLVM :: CodeGen/AMDGPU/lds-oqap-crash.ll
LLVM :: CodeGen/AMDGPU/lds-output-queue.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.i32.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll
LLVM :: CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll
LLVM :: CodeGen/AMDGPU/load-i1.ll
LLVM :: CodeGen/AMDGPU/local-atomics.ll
LLVM :: CodeGen/AMDGPU/saddo.ll
LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
LLVM :: CodeGen/AMDGPU/schedule-fs-loop-nested.ll
LLVM :: CodeGen/AMDGPU/schedule-fs-loop.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
LLVM :: CodeGen/AMDGPU/schedule-if.ll
LLVM :: CodeGen/AMDGPU/selectcc.ll
LLVM :: CodeGen/AMDGPU/setcc-opt.ll
LLVM :: CodeGen/AMDGPU/sext-eliminate.ll
LLVM :: CodeGen/AMDGPU/sext-in-reg.ll
LLVM :: CodeGen/AMDGPU/ssubo.ll
LLVM :: CodeGen/AMDGPU/uaddo.ll
LLVM :: CodeGen/AMDGPU/usubo.ll
Expected Passes : 9736
Expected Failures : 51
Unsupported Tests : 5574
Unexpected Failures: 29
Makefile:98: recipe for target 'check-local' failed
make[1]: *** [check-local] Error 1
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