[PATCH] D15331: PR25754: implement result legalization for UDIVREM8_ZEXT_HREG
A. Skrobov via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 8 05:09:30 PST 2015
tyomitch created this revision.
tyomitch added reviewers: spatel, srking.
tyomitch added a subscriber: llvm-commits.
http://reviews.llvm.org/D15331
Files:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/crash.ll
Index: test/CodeGen/X86/crash.ll
===================================================================
--- test/CodeGen/X86/crash.ll
+++ test/CodeGen/X86/crash.ll
@@ -590,3 +590,12 @@
%tmp4 = call { i32, i32 } asm sideeffect "", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %tmp3, i32 undef, i32 %tmp3, i32 %tmp1) nounwind
ret void
}
+
+define i64 @pr25754(i8 %a, i8 %c) {
+ %r1 = urem i8 %a, %c
+ %d1 = udiv i8 %a, %c
+ %r2 = zext i8 %r1 to i64
+ %d2 = zext i8 %d1 to i64
+ %ret = add i64 %r2, %d2
+ ret i64 %ret
+}
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -20058,6 +20058,16 @@
Results.push_back(V);
return;
}
+ case X86ISD::UDIVREM8_ZEXT_HREG: {
+ EVT VT = N->getValueType(1);
+ assert(VT == MVT::i64 && "Unexpected type (!= i64) on UDIVREM8_ZEXT_HREG");
+ SDVTList NodeTys = DAG.getVTList(N->getValueType(0), MVT::i32);
+ SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
+ N->getOperand(0), N->getOperand(1));
+ Results.push_back(R);
+ Results.push_back(DAG.getNode(ISD::ZERO_EXTEND, dl, VT, R.getValue(1)));
+ return;
+ }
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: {
bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
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