[llvm] r254564 - [Hexagon] Improve lowering of instructions to the MC layer
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 2 15:08:29 PST 2015
Author: kparzysz
Date: Wed Dec 2 17:08:29 2015
New Revision: 254564
URL: http://llvm.org/viewvc/llvm-project?rev=254564&view=rev
Log:
[Hexagon] Improve lowering of instructions to the MC layer
- Add extenders when necessary.
- Handle some basic relocations.
This should fix the failure in tools/clang/test/CodeGenCXX/crash.cpp
Modified:
llvm/trunk/lib/Target/Hexagon/Hexagon.h
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.h?rev=254564&r1=254563&r2=254564&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.h (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.h Wed Dec 2 17:08:29 2015
@@ -47,15 +47,8 @@
#include "llvm/Target/TargetMachine.h"
namespace llvm {
- class MachineInstr;
- class MCInst;
- class MCInstrInfo;
- class HexagonAsmPrinter;
class HexagonTargetMachine;
- void HexagonLowerToMC(const MachineInstr *MI, MCInst &MCI,
- HexagonAsmPrinter &AP);
-
/// \brief Creates a Hexagon-specific Target Transformation Info pass.
ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
} // end namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=254564&r1=254563&r2=254564&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Wed Dec 2 17:08:29 2015
@@ -56,6 +56,11 @@
using namespace llvm;
+namespace llvm {
+ void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
+ MCInst &MCB, HexagonAsmPrinter &AP);
+}
+
#define DEBUG_TYPE "asm-printer"
static cl::opt<bool> AlignCalls(
@@ -179,6 +184,7 @@ bool HexagonAsmPrinter::PrintAsmMemoryOp
///
void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst MCB = HexagonMCInstrInfo::createBundle();
+ const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
if (MI->isBundle()) {
const MachineBasicBlock* MBB = MI->getParent();
@@ -190,25 +196,23 @@ void HexagonAsmPrinter::EmitInstruction(
MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
++IgnoreCount;
else {
- HexagonLowerToMC(&*MII, MCB, *this);
+ HexagonLowerToMC(MCII, &*MII, MCB, *this);
}
}
}
else {
- HexagonLowerToMC(MI, MCB, *this);
+ HexagonLowerToMC(MCII, MI, MCB, *this);
HexagonMCInstrInfo::padEndloop(OutStreamer->getContext(), MCB);
}
// Examine the packet and try to find instructions that can be converted
// to compounds.
- HexagonMCInstrInfo::tryCompound(*Subtarget->getInstrInfo(),
- OutStreamer->getContext(), MCB);
+ HexagonMCInstrInfo::tryCompound(MCII, OutStreamer->getContext(), MCB);
// Examine the packet and convert pairs of instructions to duplex
// instructions when possible.
SmallVector<DuplexCandidate, 8> possibleDuplexes;
- possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(
- *Subtarget->getInstrInfo(), MCB);
- HexagonMCShuffle(*Subtarget->getInstrInfo(), *Subtarget,
- OutStreamer->getContext(), MCB, possibleDuplexes);
+ possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB);
+ HexagonMCShuffle(MCII, *Subtarget, OutStreamer->getContext(), MCB,
+ possibleDuplexes);
EmitToStreamer(*OutStreamer, MCB);
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=254564&r1=254563&r2=254564&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp Wed Dec 2 17:08:29 2015
@@ -26,39 +26,71 @@
using namespace llvm;
-static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol,
- HexagonAsmPrinter& Printer) {
+namespace llvm {
+ void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
+ MCInst &MCB, HexagonAsmPrinter &AP);
+}
+
+static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
+ HexagonAsmPrinter &Printer) {
MCContext &MC = Printer.OutContext;
const MCExpr *ME;
- ME = MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, MC);
+ // Populate the relocation type based on Hexagon target flags
+ // set on an operand
+ MCSymbolRefExpr::VariantKind RelocationType;
+ switch (MO.getTargetFlags()) {
+ default:
+ RelocationType = MCSymbolRefExpr::VK_None;
+ break;
+ case HexagonII::MO_PCREL:
+ RelocationType = MCSymbolRefExpr::VK_Hexagon_PCREL;
+ break;
+ case HexagonII::MO_GOT:
+ RelocationType = MCSymbolRefExpr::VK_GOT;
+ break;
+ case HexagonII::MO_LO16:
+ RelocationType = MCSymbolRefExpr::VK_Hexagon_LO16;
+ break;
+ case HexagonII::MO_HI16:
+ RelocationType = MCSymbolRefExpr::VK_Hexagon_HI16;
+ break;
+ case HexagonII::MO_GPREL:
+ RelocationType = MCSymbolRefExpr::VK_Hexagon_GPREL;
+ break;
+ }
+
+ ME = MCSymbolRefExpr::create(Symbol, RelocationType, MC);
if (!MO.isJTI() && MO.getOffset())
ME = MCBinaryExpr::createAdd(ME, MCConstantExpr::create(MO.getOffset(), MC),
MC);
- return (MCOperand::createExpr(ME));
+ return MCOperand::createExpr(ME);
}
// Create an MCInst from a MachineInstr
-void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCB,
- HexagonAsmPrinter& AP) {
- if(MI->getOpcode() == Hexagon::ENDLOOP0){
+void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
+ MCInst &MCB, HexagonAsmPrinter &AP) {
+ if (MI->getOpcode() == Hexagon::ENDLOOP0) {
HexagonMCInstrInfo::setInnerLoop(MCB);
return;
}
- if(MI->getOpcode() == Hexagon::ENDLOOP1){
+ if (MI->getOpcode() == Hexagon::ENDLOOP1) {
HexagonMCInstrInfo::setOuterLoop(MCB);
return;
}
- MCInst* MCI = new (AP.OutContext) MCInst;
+ MCInst *MCI = new (AP.OutContext) MCInst;
MCI->setOpcode(MI->getOpcode());
assert(MCI->getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&
"MCI opcode should have been set on construction");
+ bool MustExtend = false;
for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCO;
+ if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
+ MustExtend = true;
switch (MO.getType()) {
default:
@@ -107,5 +139,7 @@ void llvm::HexagonLowerToMC(MachineInstr
MCI->addOperand(MCO);
}
+ HexagonMCInstrInfo::extendIfNeeded(AP.OutContext, MCII, MCB, *MCI,
+ MustExtend);
MCB.addOperand(MCOperand::createInst(MCI));
}
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