[llvm] r254501 - Patch to fix a crash in the PowerPC back end due to ISD::ROTL and ISD::ROTR

[Nemanja Ivanovic via llvm-commits]

Author: nemanjai
Date: Wed Dec  2 04:36:24 2015
New Revision: 254501

URL: http://llvm.org/viewvc/llvm-project?rev=254501&view=rev
Log:
Patch to fix a crash in the PowerPC back end due to ISD::ROTL and ISD::ROTR
not being expanded. Test case included.

Added:
    llvm/trunk/test/CodeGen/PowerPC/rotl-rotr-crash.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=254501&r1=254500&r2=254501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Dec  2 04:36:24 2015
@@ -479,6 +479,8 @@ PPCTargetLowering::PPCTargetLowering(con
       setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
       setOperationAction(ISD::VSELECT, VT, Expand);
       setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
+      setOperationAction(ISD::ROTL, VT, Expand);
+      setOperationAction(ISD::ROTR, VT, Expand);
 
       for (MVT InnerVT : MVT::vector_valuetypes()) {
         setTruncStoreAction(VT, InnerVT, Expand);

Added: llvm/trunk/test/CodeGen/PowerPC/rotl-rotr-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/rotl-rotr-crash.ll?rev=254501&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/rotl-rotr-crash.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/rotl-rotr-crash.ll Wed Dec  2 04:36:24 2015
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8
+
+; Ensure this does not crash
+
+; Function Attrs: norecurse nounwind
+define <4 x i32> @func1 (<4 x i32> %a) {
+entry:
+  %0 = lshr <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>
+  %1 = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>
+  %2 = or <4 x i32> %1, %0
+  ret <4 x i32> %2
+}