[llvm] r254459 - AMDGPU: Disallow flat_scr in SI assembler

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Tue Dec  1 14:31:08 2015
New Revision: 254459

URL: http://llvm.org/viewvc/llvm-project?rev=254459&view=rev
Log:
AMDGPU: Disallow flat_scr in SI assembler

Added:
    llvm/trunk/test/MC/AMDGPU/flat-scratch.s
Modified:
    llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=254459&r1=254458&r2=254459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Tue Dec  1 14:31:08 2015
@@ -332,6 +332,14 @@ class AMDGPUAsmParser : public MCTargetA
 
   unsigned ForcedEncodingSize;
 
+  bool isSI() const {
+    return STI->getFeatureBits()[AMDGPU::FeatureSouthernIslands];
+  }
+
+  bool isCI() const {
+    return STI->getFeatureBits()[AMDGPU::FeatureSeaIslands];
+  }
+
   bool isVI() const {
     return getSTI().getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
   }
@@ -504,12 +512,14 @@ bool AMDGPUAsmParser::ParseRegister(unsi
   const AsmToken Tok = Parser.getTok();
   StartLoc = Tok.getLoc();
   EndLoc = Tok.getEndLoc();
+  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+
   StringRef RegName = Tok.getString();
   RegNo = getRegForName(RegName);
 
   if (RegNo) {
     Parser.Lex();
-    return false;
+    return !subtargetHasRegister(*TRI, RegNo);
   }
 
   // Match vgprs and sgprs
@@ -562,7 +572,6 @@ bool AMDGPUAsmParser::ParseRegister(unsi
     }
   }
 
-  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
   int RCID = getRegClass(IsVgpr, RegWidth);
   if (RCID == -1)
     return true;
@@ -980,9 +989,21 @@ bool AMDGPUAsmParser::ParseDirective(Asm
 
 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
                                            unsigned RegNo) const {
-  if (!isVI())
+  if (isCI())
     return true;
 
+  if (isSI()) {
+    // No flat_scr
+    switch (RegNo) {
+    case AMDGPU::FLAT_SCR:
+    case AMDGPU::FLAT_SCR_LO:
+    case AMDGPU::FLAT_SCR_HI:
+      return false;
+    default:
+      return true;
+    }
+  }
+
   // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
   // SI/CI have.
   for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true);

Added: llvm/trunk/test/MC/AMDGPU/flat-scratch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/flat-scratch.s?rev=254459&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/flat-scratch.s (added)
+++ llvm/trunk/test/MC/AMDGPU/flat-scratch.s Tue Dec  1 14:31:08 2015
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=CI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+s_mov_b64 flat_scratch, -1
+// SI: error: invalid operand for instruction
+// CI-NOT: error
+// VI-NOT: error
+
+s_mov_b32 flat_scratch_lo, -1
+// SI: error: invalid operand for instruction
+// CI-NOT: error
+// VI-NOT: error
+
+s_mov_b32 flat_scratch_hi, -1
+// SI: error: invalid operand for instruction
+// CI-NOT: error
+// VI-NOT: error
+
+
+s_mov_b64 flat_scratch_lo, -1
+// GCN: error: invalid operand for instruction
+
+s_mov_b64 flat_scratch_hi, -1
+// GCN: error: invalid operand for instruction
+
+s_mov_b32 flat_scratch, -1
+// GCN: error: invalid operand for instruction