[PATCH] D14701: [x86] add vmovss/sd missing encoding

[Igor Breger via llvm-commits]

igorb added a comment.

please add encoding tests for intel style assembler.
Is it possible to implement movss/sd load intrinsic in this patch?


================
Comment at: ../trunk/lib/Target/X86/X86InstrAVX512.td:2957
@@ +2956,3 @@
+                                   (_.VT _.RC:$src2))), IIC_SSE_MOV_S_RR>, EVEX_4V;
+  defm rm_Int : AVX512_maskable_scalar<0x10, MRMSrcMem, _, (outs _.RC:$dst), 
+                    (ins _.MemOp:$src), "v"#asm,"$src","$src",
----------------
1. dest is also source in case k[0] == 0
2. (ins _.MemOp:$src) should be  (ins _.ScalarMemOp:$src) 
3. please add mayLoad = 1 

something like

  let Constraints = "$src1 = $dst" , mayLoad = 1 in
    defm rm_Int : AVX512_maskable_3src_scalar<0x10, MRMSrcMem, _, 
                    (outs _.RC:$dst), 
                    (ins _.ScalarMemOp:$src),
                    asm,"$src","$src",
                    (_.VT (OpNode (_.VT _.RC:$src1), 
                                  (_.VT (scalar_to_vector
                                          (_.ScalarLdFrag addr:$src)))))>, EVEX;    


================
Comment at: ../trunk/lib/Target/X86/X86InstrAVX512.td:2963
@@ +2962,3 @@
+  let isCodeGenOnly = 1 in {
+    def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, _.FRC:$src2),
+               !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
----------------
You can use AVX512PI , and pass vmovss as parameter to avx512_move_scalar to avoid "v"#asm above ( in rr_Int )

================
Comment at: ../trunk/lib/Target/X86/X86InstrAVX512.td:2968
@@ +2967,3 @@
+               IIC_SSE_MOV_S_RR>, EVEX_4V;
+    def rm : SI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
+               !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
----------------
let mayLoad = 1 in


http://reviews.llvm.org/D14701