[PATCH] D15047: [Mips64] Fix extension of 32-bit integer types.

[Vladimir Radosavljevic via llvm-commits]

vradosavljevic added a comment.

In http://reviews.llvm.org/D15047#297972, @dsanders wrote:

> Could you point me at the original problem you're trying to solve? The new node appears to be doing the same job as AssertZExt and I'm fairly certain this is headed into a bigger problem we encountered back in spring.


Original problem is where operand for truncate instruction is in another basic block (foo1 function in mips64-sign-extend.ll). SelectionDAG for this case (AssertZext node was created in SelectionDAGBuilder.cpp (RegsForValue::getCopyFromRegs)):

  Optimized legalized selection DAG: BB#1 'foo:if.then'
  SelectionDAG has 13 nodes:
    t0: ch = EntryToken
              t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
            t4: i64 = AssertZext t2, ValueType:ch:i32
          t5: i32 = truncate t4
        t20: i32 = setcc t5, Constant:i32<-1>, setgt:ch
      t12: ch = brcond t0, t20, BasicBlock:ch<if.else 0x14ad3e0>
    t14: ch = br t12, BasicBlock:ch<if.then4 0x14ad318>

In this case, we need to do sign extension for (trunc (assertzext GPR64:$src)), so I changed this pattern to do sign extension. After this change, for arguments zeroext i1, zeroext i8 and zeroext i16, we got redundant SLL instruction. TruncNoExt node is used to prevent generating SLL instruction in these cases.


Repository:
  rL LLVM

http://reviews.llvm.org/D15047