[llvm] r254293 - [mips][ias] Removed MSA instructions from base architecture valid-xfail.s's.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 30 01:52:01 PST 2015
Author: dsanders
Date: Mon Nov 30 03:52:00 2015
New Revision: 254293
URL: http://llvm.org/viewvc/llvm-project?rev=254293&view=rev
Log:
[mips][ias] Removed MSA instructions from base architecture valid-xfail.s's.
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. MSA instructions are correct to fail since MSA is not enabled.
Added:
llvm/trunk/test/MC/Mips/mips32r2/invalid-msa.s
Modified:
llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s
Added: llvm/trunk/test/MC/Mips/mips32r2/invalid-msa.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/invalid-msa.s?rev=254293&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/invalid-msa.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r2/invalid-msa.s Mon Nov 30 03:52:00 2015
@@ -0,0 +1,62 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
+# RUN: -mcpu=mips32r2 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ and.v $w10,$w25,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bmnz.v $w15,$w2,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bmz.v $w13,$w11,$w21 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fclass.w $w19,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fexupl.d $w10,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fexupl.w $w12,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fexupr.d $w31,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fexupr.w $w29,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffint_s.d $w1,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffint_s.w $w16,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffint_u.d $w23,$w18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffint_u.w $w19,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffql.d $w2,$w3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffql.w $w9,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffqr.d $w25,$w24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ffqr.w $w10,$w6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fill.b $w9,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fill.h $w9,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fill.w $w31,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ flog2.d $w12,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ flog2.w $w19,$w23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ frcp.d $w12,$w4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ frcp.w $w30,$w8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ frint.d $w20,$w8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ frint.w $w11,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ frsqrt.d $w29,$w2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ frsqrt.w $w9,$w8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fsqrt.d $w3,$w1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ fsqrt.w $w5,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftint_s.d $w31,$w26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftint_s.w $w27,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftint_u.d $w5,$w31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftint_u.w $w12,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftrunc_s.d $w4,$w22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftrunc_s.w $w24,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftrunc_u.d $w20,$w25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ ftrunc_u.w $w7,$w26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ move.v $w8,$w17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nloc.b $w12,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nloc.d $w16,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nloc.h $w21,$w17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nloc.w $w17,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nlzc.b $w12,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nlzc.d $w14,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nlzc.h $w24,$w24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nlzc.w $w10,$w4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ nor.v $w20,$w20,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ or.v $w13,$w23,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pcnt.b $w30,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pcnt.d $w5,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pcnt.h $w20,$w24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pcnt.w $w22,$w20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ xor.v $w20,$w21,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s?rev=254293&r1=254292&r2=254293&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s Mon Nov 30 03:52:00 2015
@@ -28,11 +28,7 @@
adduh_r.qb $a0,$9,$12
addwc $k0,$s6,$s7
alnv.ps $f12,$f18,$f30,$12
- and.v $w10,$w25,$w29
bitrev $14,$at
- bmnz.v $w15,$w2,$w28
- bmz.v $w13,$w11,$w21
- bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -124,44 +120,9 @@
extrv_r.w $8,$ac1,$s6
extrv_rs.w $gp,$ac1,$s6
extrv_s.h $s2,$ac1,$14
- fclass.d $w14,$w27
- fclass.w $w19,$w28
- fexupl.d $w10,$w29
- fexupl.w $w12,$w27
- fexupr.d $w31,$w15
- fexupr.w $w29,$w12
- ffint_s.d $w1,$w30
- ffint_s.w $w16,$w14
- ffint_u.d $w23,$w18
- ffint_u.w $w19,$w12
- ffql.d $w2,$w3
- ffql.w $w9,$w0
- ffqr.d $w25,$w24
- ffqr.w $w10,$w6
- fill.b $w9,$v1
- fill.h $w9,$8
- fill.w $w31,$15
- flog2.d $w12,$w16
- flog2.w $w19,$w23
floor.l.d $f26,$f7
floor.l.s $f12,$f5
fork $s2,$8,$a0
- frcp.d $w12,$w4
- frcp.w $w30,$w8
- frint.d $w20,$w8
- frint.w $w11,$w29
- frsqrt.d $w29,$w2
- frsqrt.w $w9,$w8
- fsqrt.d $w3,$w1
- fsqrt.w $w5,$w15
- ftint_s.d $w31,$w26
- ftint_s.w $w27,$w14
- ftint_u.d $w5,$w31
- ftint_u.w $w12,$w29
- ftrunc_s.d $w4,$w22
- ftrunc_s.w $w24,$w7
- ftrunc_u.d $w20,$w25
- ftrunc_u.w $w7,$w26
insv $s2,$at
iret
lbe $14,122($9)
@@ -184,7 +145,6 @@
mflo $9,$ac2
modsub $a3,$12,$a3
mov.ps $f22,$f17
- move.v $w8,$w17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
@@ -210,23 +170,9 @@
mulsa.w.ph $ac1,$s4,$s6
mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
- nloc.b $w12,$w30
- nloc.d $w16,$w7
- nloc.h $w21,$w17
- nloc.w $w17,$w16
- nlzc.b $w12,$w7
- nlzc.d $w14,$w14
- nlzc.h $w24,$w24
- nlzc.w $w10,$w4
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- nor.v $w20,$w20,$w15
- or.v $w13,$w23,$w12
packrl.ph $ra,$24,$14
- pcnt.b $w30,$w15
- pcnt.d $w5,$w16
- pcnt.h $w20,$w24
- pcnt.w $w22,$w20
pick.ph $ra,$a2,$gp
pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
@@ -304,5 +250,4 @@
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
wrpgpr $zero,$13
- xor.v $w20,$w21,$w30
yield $v1,$s0
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s?rev=254293&r1=254292&r2=254293&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s Mon Nov 30 03:52:00 2015
@@ -28,11 +28,7 @@
adduh_r.qb $a0,$9,$12
addwc $k0,$s6,$s7
alnv.ps $f12,$f18,$f30,$12
- and.v $w10,$w25,$w29
bitrev $14,$at
- bmnz.v $w15,$w2,$w28
- bmz.v $w13,$w11,$w21
- bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -124,44 +120,9 @@
extrv_r.w $8,$ac1,$s6
extrv_rs.w $gp,$ac1,$s6
extrv_s.h $s2,$ac1,$14
- fclass.d $w14,$w27
- fclass.w $w19,$w28
- fexupl.d $w10,$w29
- fexupl.w $w12,$w27
- fexupr.d $w31,$w15
- fexupr.w $w29,$w12
- ffint_s.d $w1,$w30
- ffint_s.w $w16,$w14
- ffint_u.d $w23,$w18
- ffint_u.w $w19,$w12
- ffql.d $w2,$w3
- ffql.w $w9,$w0
- ffqr.d $w25,$w24
- ffqr.w $w10,$w6
- fill.b $w9,$v1
- fill.h $w9,$8
- fill.w $w31,$15
- flog2.d $w12,$w16
- flog2.w $w19,$w23
floor.l.d $f26,$f7
floor.l.s $f12,$f5
fork $s2,$8,$a0
- frcp.d $w12,$w4
- frcp.w $w30,$w8
- frint.d $w20,$w8
- frint.w $w11,$w29
- frsqrt.d $w29,$w2
- frsqrt.w $w9,$w8
- fsqrt.d $w3,$w1
- fsqrt.w $w5,$w15
- ftint_s.d $w31,$w26
- ftint_s.w $w27,$w14
- ftint_u.d $w5,$w31
- ftint_u.w $w12,$w29
- ftrunc_s.d $w4,$w22
- ftrunc_s.w $w24,$w7
- ftrunc_u.d $w20,$w25
- ftrunc_u.w $w7,$w26
insv $s2,$at
iret
lbe $14,122($9)
@@ -184,7 +145,6 @@
mflo $9,$ac2
modsub $a3,$12,$a3
mov.ps $f22,$f17
- move.v $w8,$w17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
@@ -210,23 +170,9 @@
mulsa.w.ph $ac1,$s4,$s6
mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
- nloc.b $w12,$w30
- nloc.d $w16,$w7
- nloc.h $w21,$w17
- nloc.w $w17,$w16
- nlzc.b $w12,$w7
- nlzc.d $w14,$w14
- nlzc.h $w24,$w24
- nlzc.w $w10,$w4
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- nor.v $w20,$w20,$w15
- or.v $w13,$w23,$w12
packrl.ph $ra,$24,$14
- pcnt.b $w30,$w15
- pcnt.d $w5,$w16
- pcnt.h $w20,$w24
- pcnt.w $w22,$w20
pick.ph $ra,$a2,$gp
pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
@@ -304,5 +250,4 @@
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
wrpgpr $zero,$13
- xor.v $w20,$w21,$w30
yield $v1,$s0
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s?rev=254293&r1=254292&r2=254293&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s Mon Nov 30 03:52:00 2015
@@ -28,11 +28,7 @@
adduh_r.qb $a0,$9,$12
addwc $k0,$s6,$s7
alnv.ps $f12,$f18,$f30,$12
- and.v $w10,$w25,$w29
bitrev $14,$at
- bmnz.v $w15,$w2,$w28
- bmz.v $w13,$w11,$w21
- bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -124,44 +120,9 @@
extrv_r.w $8,$ac1,$s6
extrv_rs.w $gp,$ac1,$s6
extrv_s.h $s2,$ac1,$14
- fclass.d $w14,$w27
- fclass.w $w19,$w28
- fexupl.d $w10,$w29
- fexupl.w $w12,$w27
- fexupr.d $w31,$w15
- fexupr.w $w29,$w12
- ffint_s.d $w1,$w30
- ffint_s.w $w16,$w14
- ffint_u.d $w23,$w18
- ffint_u.w $w19,$w12
- ffql.d $w2,$w3
- ffql.w $w9,$w0
- ffqr.d $w25,$w24
- ffqr.w $w10,$w6
- fill.b $w9,$v1
- fill.h $w9,$8
- fill.w $w31,$15
- flog2.d $w12,$w16
- flog2.w $w19,$w23
floor.l.d $f26,$f7
floor.l.s $f12,$f5
fork $s2,$8,$a0
- frcp.d $w12,$w4
- frcp.w $w30,$w8
- frint.d $w20,$w8
- frint.w $w11,$w29
- frsqrt.d $w29,$w2
- frsqrt.w $w9,$w8
- fsqrt.d $w3,$w1
- fsqrt.w $w5,$w15
- ftint_s.d $w31,$w26
- ftint_s.w $w27,$w14
- ftint_u.d $w5,$w31
- ftint_u.w $w12,$w29
- ftrunc_s.d $w4,$w22
- ftrunc_s.w $w24,$w7
- ftrunc_u.d $w20,$w25
- ftrunc_u.w $w7,$w26
insv $s2,$at
iret
lbe $14,122($9)
@@ -184,7 +145,6 @@
mflo $9,$ac2
modsub $a3,$12,$a3
mov.ps $f22,$f17
- move.v $w8,$w17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
@@ -210,23 +170,9 @@
mulsa.w.ph $ac1,$s4,$s6
mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
- nloc.b $w12,$w30
- nloc.d $w16,$w7
- nloc.h $w21,$w17
- nloc.w $w17,$w16
- nlzc.b $w12,$w7
- nlzc.d $w14,$w14
- nlzc.h $w24,$w24
- nlzc.w $w10,$w4
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- nor.v $w20,$w20,$w15
- or.v $w13,$w23,$w12
packrl.ph $ra,$24,$14
- pcnt.b $w30,$w15
- pcnt.d $w5,$w16
- pcnt.h $w20,$w24
- pcnt.w $w22,$w20
pick.ph $ra,$a2,$gp
pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
@@ -304,5 +250,4 @@
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
wrpgpr $zero,$13
- xor.v $w20,$w21,$w30
yield $v1,$s0
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s?rev=254293&r1=254292&r2=254293&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s Mon Nov 30 03:52:00 2015
@@ -31,11 +31,7 @@
alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12
- and.v $w10,$w25,$w29
bitrev $14,$at
- bmnz.v $w15,$w2,$w28
- bmz.v $w13,$w11,$w21
- bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -126,43 +122,7 @@
extrv_r.w $8,$ac1,$s6
extrv_rs.w $gp,$ac1,$s6
extrv_s.h $s2,$ac1,$14
- fclass.d $w14,$w27
- fclass.w $w19,$w28
- fexupl.d $w10,$w29
- fexupl.w $w12,$w27
- fexupr.d $w31,$w15
- fexupr.w $w29,$w12
- ffint_s.d $w1,$w30
- ffint_s.w $w16,$w14
- ffint_u.d $w23,$w18
- ffint_u.w $w19,$w12
- ffql.d $w2,$w3
- ffql.w $w9,$w0
- ffqr.d $w25,$w24
- ffqr.w $w10,$w6
- fill.b $w9,$v1
- fill.d $w28,$8
- fill.h $w9,$8
- fill.w $w31,$15
- flog2.d $w12,$w16
- flog2.w $w19,$w23
fork $s2,$8,$a0
- frcp.d $w12,$w4
- frcp.w $w30,$w8
- frint.d $w20,$w8
- frint.w $w11,$w29
- frsqrt.d $w29,$w2
- frsqrt.w $w9,$w8
- fsqrt.d $w3,$w1
- fsqrt.w $w5,$w15
- ftint_s.d $w31,$w26
- ftint_s.w $w27,$w14
- ftint_u.d $w5,$w31
- ftint_u.w $w12,$w29
- ftrunc_s.d $w4,$w22
- ftrunc_s.w $w24,$w7
- ftrunc_u.d $w20,$w25
- ftrunc_u.w $w7,$w26
insv $s2,$at
iret
lbe $14,122($9)
@@ -212,23 +172,9 @@
mulsa.w.ph $ac1,$s4,$s6
mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
- nloc.b $w12,$w30
- nloc.d $w16,$w7
- nloc.h $w21,$w17
- nloc.w $w17,$w16
- nlzc.b $w12,$w7
- nlzc.d $w14,$w14
- nlzc.h $w24,$w24
- nlzc.w $w10,$w4
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- nor.v $w20,$w20,$w15
- or.v $w13,$w23,$w12
packrl.ph $ra,$24,$14
- pcnt.b $w30,$w15
- pcnt.d $w5,$w16
- pcnt.h $w20,$w24
- pcnt.w $w22,$w20
pick.ph $ra,$a2,$gp
pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
@@ -302,5 +248,4 @@
tlbinv
tlbinvf
wrpgpr $zero,$13
- xor.v $w20,$w21,$w30
yield $v1,$s0
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s?rev=254293&r1=254292&r2=254293&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s Mon Nov 30 03:52:00 2015
@@ -31,11 +31,7 @@
alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12
- and.v $w10,$w25,$w29
bitrev $14,$at
- bmnz.v $w15,$w2,$w28
- bmz.v $w13,$w11,$w21
- bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -126,43 +122,7 @@
extrv_r.w $8,$ac1,$s6
extrv_rs.w $gp,$ac1,$s6
extrv_s.h $s2,$ac1,$14
- fclass.d $w14,$w27
- fclass.w $w19,$w28
- fexupl.d $w10,$w29
- fexupl.w $w12,$w27
- fexupr.d $w31,$w15
- fexupr.w $w29,$w12
- ffint_s.d $w1,$w30
- ffint_s.w $w16,$w14
- ffint_u.d $w23,$w18
- ffint_u.w $w19,$w12
- ffql.d $w2,$w3
- ffql.w $w9,$w0
- ffqr.d $w25,$w24
- ffqr.w $w10,$w6
- fill.b $w9,$v1
- fill.d $w28,$8
- fill.h $w9,$8
- fill.w $w31,$15
- flog2.d $w12,$w16
- flog2.w $w19,$w23
fork $s2,$8,$a0
- frcp.d $w12,$w4
- frcp.w $w30,$w8
- frint.d $w20,$w8
- frint.w $w11,$w29
- frsqrt.d $w29,$w2
- frsqrt.w $w9,$w8
- fsqrt.d $w3,$w1
- fsqrt.w $w5,$w15
- ftint_s.d $w31,$w26
- ftint_s.w $w27,$w14
- ftint_u.d $w5,$w31
- ftint_u.w $w12,$w29
- ftrunc_s.d $w4,$w22
- ftrunc_s.w $w24,$w7
- ftrunc_u.d $w20,$w25
- ftrunc_u.w $w7,$w26
insv $s2,$at
iret
lbe $14,122($9)
@@ -212,23 +172,9 @@
mulsa.w.ph $ac1,$s4,$s6
mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
- nloc.b $w12,$w30
- nloc.d $w16,$w7
- nloc.h $w21,$w17
- nloc.w $w17,$w16
- nlzc.b $w12,$w7
- nlzc.d $w14,$w14
- nlzc.h $w24,$w24
- nlzc.w $w10,$w4
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- nor.v $w20,$w20,$w15
- or.v $w13,$w23,$w12
packrl.ph $ra,$24,$14
- pcnt.b $w30,$w15
- pcnt.d $w5,$w16
- pcnt.h $w20,$w24
- pcnt.w $w22,$w20
pick.ph $ra,$a2,$gp
pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
@@ -302,5 +248,4 @@
tlbinv
tlbinvf
wrpgpr $zero,$13
- xor.v $w20,$w21,$w30
yield $v1,$s0
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s?rev=254293&r1=254292&r2=254293&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s Mon Nov 30 03:52:00 2015
@@ -31,11 +31,7 @@
alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12
- and.v $w10,$w25,$w29
bitrev $14,$at
- bmnz.v $w15,$w2,$w28
- bmz.v $w13,$w11,$w21
- bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -126,43 +122,7 @@
extrv_r.w $8,$ac1,$s6
extrv_rs.w $gp,$ac1,$s6
extrv_s.h $s2,$ac1,$14
- fclass.d $w14,$w27
- fclass.w $w19,$w28
- fexupl.d $w10,$w29
- fexupl.w $w12,$w27
- fexupr.d $w31,$w15
- fexupr.w $w29,$w12
- ffint_s.d $w1,$w30
- ffint_s.w $w16,$w14
- ffint_u.d $w23,$w18
- ffint_u.w $w19,$w12
- ffql.d $w2,$w3
- ffql.w $w9,$w0
- ffqr.d $w25,$w24
- ffqr.w $w10,$w6
- fill.b $w9,$v1
- fill.d $w28,$8
- fill.h $w9,$8
- fill.w $w31,$15
- flog2.d $w12,$w16
- flog2.w $w19,$w23
fork $s2,$8,$a0
- frcp.d $w12,$w4
- frcp.w $w30,$w8
- frint.d $w20,$w8
- frint.w $w11,$w29
- frsqrt.d $w29,$w2
- frsqrt.w $w9,$w8
- fsqrt.d $w3,$w1
- fsqrt.w $w5,$w15
- ftint_s.d $w31,$w26
- ftint_s.w $w27,$w14
- ftint_u.d $w5,$w31
- ftint_u.w $w12,$w29
- ftrunc_s.d $w4,$w22
- ftrunc_s.w $w24,$w7
- ftrunc_u.d $w20,$w25
- ftrunc_u.w $w7,$w26
insv $s2,$at
iret
lbe $14,122($9)
@@ -212,23 +172,9 @@
mulsa.w.ph $ac1,$s4,$s6
mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
- nloc.b $w12,$w30
- nloc.d $w16,$w7
- nloc.h $w21,$w17
- nloc.w $w17,$w16
- nlzc.b $w12,$w7
- nlzc.d $w14,$w14
- nlzc.h $w24,$w24
- nlzc.w $w10,$w4
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- nor.v $w20,$w20,$w15
- or.v $w13,$w23,$w12
packrl.ph $ra,$24,$14
- pcnt.b $w30,$w15
- pcnt.d $w5,$w16
- pcnt.h $w20,$w24
- pcnt.w $w22,$w20
pick.ph $ra,$a2,$gp
pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
@@ -302,5 +248,4 @@
tlbinv
tlbinvf
wrpgpr $zero,$13
- xor.v $w20,$w21,$w30
yield $v1,$s0
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