[PATCH] D15017: [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register

[Oliver Stannard via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL254155: [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register (authored by olista01).

Changed prior to commit:
  http://reviews.llvm.org/D15017?vs=41238&id=41253#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15017

Files:
  llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
  llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s
  llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt

Index: llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+
+[0x43,0x07,0x38,0xd5]
+# CHECK: mrs x3, ID_AA64MMFR2_EL1
Index: llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s
+++ llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+  mrs x3, id_aa64mmfr2_el1
+// CHECK: mrs x3, ID_AA64MMFR2_EL1       // encoding: [0x43,0x07,0x38,0xd5]
+// ERROR: error: expected readable system register
Index: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
===================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -594,6 +594,7 @@
     ID_A64ISAR1_EL1   = 0xc031, // 11  000  0000  0110  001
     ID_A64MMFR0_EL1   = 0xc038, // 11  000  0000  0111  000
     ID_A64MMFR1_EL1   = 0xc039, // 11  000  0000  0111  001
+    ID_A64MMFR2_EL1   = 0xc03a, // 11  000  0000  0111  010
     MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
Index: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -192,6 +192,7 @@
   {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
   {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
   {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
+  {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}},
   {"mvfr0_el1", MVFR0_EL1, {}},
   {"mvfr1_el1", MVFR1_EL1, {}},
   {"mvfr2_el1", MVFR2_EL1, {}},


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