[PATCH] D15016: [AArch64] Add ARMv8.2-A persistent memory instruction

[Oliver Stannard via llvm-commits]

olista01 created this revision.
olista01 added a reviewer: t.p.northover.
olista01 added a subscriber: llvm-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

ARMv8.2-A adds the "dc cvap" instruction, which is a system instruction
that cleans caches to the point of persistence (for systems that have
persistent memory). It is a required part of ARMv8.2-A, so no additional
subtarget features are required.

Repository:
  rL LLVM

http://reviews.llvm.org/D15016

Files:
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
  lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
  test/MC/AArch64/armv8.2a-persistent-memory.s
  test/MC/Disassembler/AArch64/armv8.2a-persistent-memory.txt

Index: test/MC/Disassembler/AArch64/armv8.2a-persistent-memory.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AArch64/armv8.2a-persistent-memory.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck --check-prefix=NO_V82 %s
+
+[0x27,0x7c,0x0b,0xd5]
+# CHECK: dc cvap, x7
+# NO_V82: sys #3, c7, c12, #1, x7
Index: test/MC/AArch64/armv8.2a-persistent-memory.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/armv8.2a-persistent-memory.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+  dc cvap, x7
+// CHECK: dc cvap, x7   // encoding: [0x27,0x7c,0x0b,0xd5]
+// ERROR: error: DC CVAP requires ARMv8.2a
Index: lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
===================================================================
--- lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
+++ lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
@@ -48,7 +48,8 @@
                                      unsigned AltIdx = AArch64::NoRegAltName);
 
 protected:
-  bool printSysAlias(const MCInst *MI, raw_ostream &O);
+  bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
+                     raw_ostream &O);
   // Operand printers
   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
Index: lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
===================================================================
--- lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
+++ lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
@@ -55,7 +55,7 @@
   unsigned Opcode = MI->getOpcode();
 
   if (Opcode == AArch64::SYSxt)
-    if (printSysAlias(MI, O)) {
+    if (printSysAlias(MI, STI, O)) {
       printAnnotation(O, Annot);
       return;
     }
@@ -674,7 +674,9 @@
   AArch64InstPrinter::printInst(MI, O, Annot, STI);
 }
 
-bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
+bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
+                                       const MCSubtargetInfo &STI,
+                                       raw_ostream &O) {
 #ifndef NDEBUG
   unsigned Opcode = MI->getOpcode();
   assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
@@ -729,6 +731,11 @@
       if (Op1Val == 3 && Op2Val == 1)
         Asm = "dc\tcvau";
       break;
+    case 12:
+      if (Op1Val == 3 && Op2Val == 1 &&
+          (STI.getFeatureBits()[AArch64::HasV8_2aOps]))
+        Asm = "dc\tcvap";
+      break;
     case 14:
       if (Op1Val == 3 && Op2Val == 1)
         Asm = "dc\tcivac";
Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2467,6 +2467,13 @@
     } else if (!Op.compare_lower("cisw")) {
       // SYS #0, C7, C14, #2
       SYS_ALIAS(0, 7, 14, 2);
+    } else if (!Op.compare_lower("cvap")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #3, C7, C12, #1
+        SYS_ALIAS(3, 7, 12, 1);
+      } else {
+        return TokError("DC CVAP requires ARMv8.2a");
+      }
     } else {
       return TokError("invalid operand for DC instruction");
     }


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