[llvm] r254137 - Add type constraints to masked_load/masked_store to ensure the mask vector has the same number of elements as the other vectors.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Nov 26 00:30:42 2015
New Revision: 254137

URL: http://llvm.org/viewvc/llvm-project?rev=254137&view=rev
Log:
Add type constraints to masked_load/masked_store to ensure the mask vector has the same number of elements as the other vectors.

Modified:
    llvm/trunk/include/llvm/Target/TargetSelectionDAG.td

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=254137&r1=254136&r2=254137&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu Nov 26 00:30:42 2015
@@ -205,11 +205,12 @@ def SDTIStore : SDTypeProfile<1, 3, [
 ]>;
 
 def SDTMaskedStore: SDTypeProfile<0, 3, [       // masked store
-  SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>
+  SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2>
 ]>;
 
 def SDTMaskedLoad: SDTypeProfile<1, 3, [       // masked load
-  SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>
+  SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>,
+  SDTCisSameNumEltsAs<0, 2>
 ]>;
 
 def SDTMaskedGather: SDTypeProfile<2, 3, [       // masked gather