[llvm] r254106 - [WebAssembly] Fix inline asm support for i64 operands.
Dan Gohman via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 25 14:28:50 PST 2015
Author: djg
Date: Wed Nov 25 16:28:50 2015
New Revision: 254106
URL: http://llvm.org/viewvc/llvm-project?rev=254106&view=rev
Log:
[WebAssembly] Fix inline asm support for i64 operands.
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/test/CodeGen/WebAssembly/inline-asm.ll
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=254106&r1=254105&r2=254106&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Wed Nov 25 16:28:50 2015
@@ -220,7 +220,11 @@ WebAssemblyTargetLowering::getRegForInli
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
- return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT == MVT::i32)
+ return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT == MVT::i64)
+ return std::make_pair(0U, &WebAssembly::I64RegClass);
+ break;
default:
break;
}
Modified: llvm/trunk/test/CodeGen/WebAssembly/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/inline-asm.ll?rev=254106&r1=254105&r2=254106&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/inline-asm.ll Wed Nov 25 16:28:50 2015
@@ -43,6 +43,19 @@ entry:
ret i32 %0
}
+; CHECK-LABEL: foo_i64:
+; CHECK-NEXT: .param i64{{$}}
+; CHECK-NEXT: .result i64{{$}}
+; CHECK-NEXT: #APP{{$}}
+; CHECK-NEXT: # $0 = aaa($0){{$}}
+; CHECK-NEXT: #NO_APP{{$}}
+; CHECK-NEXT: return $0{{$}}
+define i64 @foo_i64(i64 %r) {
+entry:
+ %0 = tail call i64 asm sideeffect "# $0 = aaa($1)", "=r,r"(i64 %r) #0, !srcloc !0
+ ret i64 %0
+}
+
attributes #0 = { nounwind }
!0 = !{i32 47}
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