[PATCH] D14967: ScheduleDAGInstrs: Move LiveIntervals field to ScheduleDAGMI

Matthias Braun via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 24 14:01:07 PST 2015


MatzeB created this revision.
MatzeB added a reviewer: atrick.
MatzeB added a subscriber: llvm-commits.
MatzeB set the repository for this revision to rL LLVM.

This patch is possible with the new ScheduleDAG construction algorithm which does not depend on liveness anymore.

Now that ScheduleDAGInstrs doesn't need it anymore we can move the field
down the class hierarcy to ScheduleDAGMI.

Repository:
  rL LLVM

http://reviews.llvm.org/D14967

Files:
  include/llvm/CodeGen/MachineScheduler.h
  include/llvm/CodeGen/ScheduleDAGInstrs.h
  lib/CodeGen/ScheduleDAGInstrs.cpp

Index: lib/CodeGen/ScheduleDAGInstrs.cpp
===================================================================
--- lib/CodeGen/ScheduleDAGInstrs.cpp
+++ lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -51,9 +51,8 @@
 
 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
                                      const MachineLoopInfo *mli,
-                                     LiveIntervals *LIS,
                                      bool RemoveKillFlags)
-    : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(LIS),
+    : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
       RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false),
       TrackLaneMasks(false), FirstDbgValue(nullptr) {
   DbgValues.clear();
Index: include/llvm/CodeGen/ScheduleDAGInstrs.h
===================================================================
--- include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -26,7 +26,6 @@
   class MachineFrameInfo;
   class MachineLoopInfo;
   class MachineDominatorTree;
-  class LiveIntervals;
   class RegPressureTracker;
   class PressureDiffs;
 
@@ -92,9 +91,6 @@
     const MachineLoopInfo *MLI;
     const MachineFrameInfo *MFI;
 
-    /// Live Intervals provides reaching defs in preRA scheduling.
-    LiveIntervals *LIS;
-
     /// TargetSchedModel provides an interface to the machine model.
     TargetSchedModel SchedModel;
 
@@ -172,14 +168,10 @@
   public:
     explicit ScheduleDAGInstrs(MachineFunction &mf,
                                const MachineLoopInfo *mli,
-                               LiveIntervals *LIS = nullptr,
                                bool RemoveKillFlags = false);
 
     ~ScheduleDAGInstrs() override {}
 
-    /// \brief Expose LiveIntervals for use in DAG mutators and such.
-    LiveIntervals *getLIS() const { return LIS; }
-
     /// \brief Get the machine model for instruction scheduling.
     const TargetSchedModel *getSchedModel() const { return &SchedModel; }
 
Index: include/llvm/CodeGen/MachineScheduler.h
===================================================================
--- include/llvm/CodeGen/MachineScheduler.h
+++ include/llvm/CodeGen/MachineScheduler.h
@@ -228,6 +228,7 @@
 class ScheduleDAGMI : public ScheduleDAGInstrs {
 protected:
   AliasAnalysis *AA;
+  LiveIntervals *LIS;
   std::unique_ptr<MachineSchedStrategy> SchedImpl;
 
   /// Topo - A topological ordering for SUnits which permits fast IsReachable
@@ -255,17 +256,21 @@
 public:
   ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
                 bool RemoveKillFlags)
-      : ScheduleDAGInstrs(*C->MF, C->MLI, C->LIS, RemoveKillFlags),
-        AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
-        CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
+      : ScheduleDAGInstrs(*C->MF, C->MLI, RemoveKillFlags), AA(C->AA),
+        LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU),
+        CurrentTop(), CurrentBottom(), NextClusterPred(nullptr),
+        NextClusterSucc(nullptr) {
 #ifndef NDEBUG
     NumInstrsScheduled = 0;
 #endif
   }
 
   // Provide a vtable anchor
   ~ScheduleDAGMI() override;
 
+  // Returns LiveIntervals instance for use in DAG mutators and such.
+  LiveIntervals *getLIS() const { return LIS; }
+
   /// Return true if this DAG supports VReg liveness and RegPressure.
   virtual bool hasVRegLiveness() const { return false; }
 


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