[PATCH] D14902: [AArch64] Promote loads from stored

[Chad Rosier via llvm-commits]

mcrosier added inline comments.

================
Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:1057
@@ +1056,3 @@
+        isLdOffsetInRangeOfStored(FirstMI, MI) &&
+        !ModifiedRegs[getLdStRegOp(MI).getReg()]) {
+      Stored = MBBI;
----------------
What if the store instruction modifies the base register (e.g., pre-/post-index)?  I'm guessing the isMatchingStore makes that check unnecessary because it doesn't check for pre-/post-index versions of the store.

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Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:1496
@@ +1495,3 @@
+    ++NumLoadsFromStoredPromoted;
+    // Promote the load. Keeping the iterator straight is a
+    // pain, so we let the merge routine tell us what the next instruction
----------------
Maximize 80-column.


http://reviews.llvm.org/D14902