[PATCH] D10970: [mips] Promote the result of SETCC nodes to GPR width.

[Vasileios Kalintiris via llvm-commits]

vkalintiris added inline comments.

================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:1707-1708
@@ +1706,4 @@
+                              Op.getValueType());
+  assert(((VT == MVT::i32) || (VT == MVT::i64)) &&
+         "Result type of SETCC is not i32 or i64.");
+
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I forgot to remove this before creating the review request. I wrote the assert when I was developing this patch because it fired in one case.

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Comment at: test/CodeGen/Mips/atomic.ll:351
@@ -348,1 +350,3 @@
+; MIPS64-ANY:    sltiu   $[[R21:[0-9]+]],  $[[R20]], 1
+; MIPS64-ANY:    sll     $2, $[[R21]], 0
 }
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In this case, it's a truncation from i64 to i32. There's a problem with RetCC_MipsN at the moment and we use V0 instead of V0_64. We'll have to fix this in a follow-up patch. The same is true for the rest of the truncations (SLLs) in rest of your questions.

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Comment at: test/CodeGen/Mips/cmov.ll:469-472
@@ -484,6 +468,6 @@
 
 ; FIXME: The 32-bit versions of this test are too complicated to reasonably
 ;        match at the moment. They do show some missing optimizations though
 ;        such as:
 ;           (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)
 
----------------
No, I added two new test cases.


http://reviews.llvm.org/D10970