[llvm] r253867 - [Hexagon] Update instruction formats
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 23 06:09:27 PST 2015
Author: kparzysz
Date: Mon Nov 23 08:09:26 2015
New Revision: 253867
URL: http://llvm.org/viewvc/llvm-project?rev=253867&view=rev
Log:
[Hexagon] Update instruction formats
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=253867&r1=253866&r2=253867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Mon Nov 23 08:09:26 2015
@@ -21,8 +21,6 @@ def TypeMEMOP : IType<9>;
def TypeNV : IType<10>;
def TypeDUPLEX : IType<11>;
def TypeCOMPOUND : IType<12>;
-def TypeAG_VX : IType<28>;
-def TypeAG_VM : IType<29>;
def TypePREFIX : IType<30>;
// Duplex Instruction Class Declaration
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td?rev=253867&r1=253866&r2=253867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td Mon Nov 23 08:09:26 2015
@@ -41,175 +41,175 @@ let validSubTargets = HasV60SubT in
{
class CVI_VA_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VA>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VA_DV_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VA_DV>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX_LONG>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_Resource_late<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX_LATE>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
Requires<[HasV60T, UseHVX]>;
class CVI_VX_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX_DV>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Slot2_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX_DV_SLOT2>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX_DV_LONG>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VP_LONG>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_VS_Resource_early<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VP_VS_EARLY>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_VS_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VP_VS_LONG>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_VS_Resource_long_early<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VP_VS_LONG_EARLY>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VS_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VS>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VINLANESAT_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VINLANESAT>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VINLANESAT>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VS_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VS>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_LD_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_LD>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_LD_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_LD>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_TMP_LD_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_TMP_LD>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_TMP_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_TMP_LD_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_TMP_LD>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_TMP_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_CUR_LD_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_CUR_LD>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_CUR_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_VP_LDU_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_VP_LDU>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_VP_LDU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_VP_LDU_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_VP_LDU>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_VP_LDU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_ST_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_ST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_ST_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_ST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_NEW_ST_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_NEW_ST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_NEW_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_NEW_ST_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_NEW_ST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_NEW_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_STU_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_STU>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_STU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_STU_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VM_STU>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_STU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_HIST_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_HIST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
}
@@ -218,19 +218,19 @@ let validSubTargets = HasV60SubT in
{
class CVI_VA_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VA>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_VX_DV>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
Requires<[HasV60T, UseHVX]>;
class CVI_HIST_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = PSEUDO>
+ InstrItinClass itin = CVI_HIST>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
Requires<[HasV60T, UseHVX]>;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=253867&r1=253866&r2=253867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Mon Nov 23 08:09:26 2015
@@ -3302,16 +3302,22 @@ defm L4_return: LD_MISC_L4_RETURN <"deal
let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
+ let isExtended = 1, opExtendable = 0 in
+ def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
}
// Restore registers and dealloc frame before a tail call.
let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
+ let isExtended = 1, opExtendable = 0 in
+ def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
}
// Save registers function call.
let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
+ let isExtended = 1, opExtendable = 0 in
+ def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td?rev=253867&r1=253866&r2=253867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td Mon Nov 23 08:09:26 2015
@@ -17,6 +17,8 @@ include "HexagonScheduleV4.td"
include "HexagonScheduleV55.td"
//===----------------------------------------------------------------------===//
-// V4 Machine Info -
+// V60 Machine Info -
//===----------------------------------------------------------------------===//
+include "HexagonScheduleV60.td"
+
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