[PATCH] D14713: [ELF2] - Optimization for R_X86_64_GOTTPOFF relocation.

[George Rimar via llvm-commits]

grimar added inline comments.

================
Comment at: ELF/Target.cpp:375-378
@@ +374,6 @@
+  bool IsMovOp = *Instruct == 0x8b;
+  if (*Prefix == 0x4c)
+    *Prefix = IsMovOp ? 0x49 : 0x4D;
+  *Instruct = IsMovOp ? 0xc7 : 0x8d;
+  *RegSlot = IsMovOp ? (0xc0 | Reg) : (0x80 | Reg | (Reg << 3));
+  relocateOne(Loc, BufEnd, R_X86_64_TPOFF32, P, SA);
----------------
grimar wrote:
> ruiu wrote:
> > Does this handle SP register?
> No. As I wrote in comments it will enlarge that code, but I can do that. Should I ?
With handling SP/r12 registers will be something like next:
(generates 
48 81 c4 f8 ff ff ff add  $0xfffffffffffffff8,%rsp for addq tls0 at GOTTPOFF(%rip), %rsp
49 81 c4 f8 ff ff ff add  $0xfffffffffffffff8,%r12 for addq tls0 at GOTTPOFF(%rip), %r12)

```
void X86_64TargetInfo::relocateTlsOptimize(uint8_t *Loc, uint8_t *BufEnd,
                                           uint32_t Type, uint64_t P,
                                           uint64_t SA) const {
  uint8_t *Prefix = &Loc[-3];
  uint8_t *Inst = &Loc[-2];
  uint8_t *RegSlot = &Loc[-1];
  uint8_t Reg = (Loc[-1]) >> 3;
  bool IsAdd = !(*Inst == 0x8b || Reg == 4);
  if (Reg == 4 && !IsAdd)
    *Inst = 0x81;
  else
    *Inst = IsAdd ? 0x8d : 0xc7;
  if (*Prefix == 0x4c)
    *Prefix = IsAdd ? 0x4d : 0x49;
  *RegSlot = IsAdd ? (0x80 | Reg | (Reg << 3)) : (0xc0 | Reg);

  relocateOne(Loc, BufEnd, R_X86_64_TPOFF32, P, SA);
}
```


http://reviews.llvm.org/D14713