[PATCH] D14750: Support for function-live-in virtual registers

[Dan Gohman via llvm-commits]

sunfish created this revision.
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Herald added subscribers: dschuff, jfb, qcolombet, MatzeB.

The WebAssembly virtual ISA has an infinite virtual register set, and function arguments are passed in registers. We're currently using pseudo-instructions (eg. ARGUMENT_i32) inserted into the entry block which provide register definitions, however it's awkward to prevent other instructions from being scheduled above them, and subsequently to prevent register coloring from clobbering the argument registers before they are properly defined.

The patch here provides a different option: make it possible to have live-in virtual registers. This way, their liveness is naturally correct and liveness-oriented passes tend to handle them correctly by default, and it eliminates the need for the awkward pseudo-instructions.

The tricky part is that such virtual registers no longer have a defining instruction, which some parts of CodeGen currently assume, particularly the passes that operate on SSA form. To address this, this patch adds a getVRegDefMBB(), for use when code is calling getVRegDef() just to get the block the register is defined in (and this is what motivates making MachineRegisterInfo's MachineFunction non-const), and adds special checks when code is calling getVRegDef() because it actually wants the defining instruction.

Repository:
  rL LLVM

http://reviews.llvm.org/D14750

Files:
  include/llvm/CodeGen/MachineRegisterInfo.h
  lib/CodeGen/LiveRangeCalc.cpp
  lib/CodeGen/LiveVariables.cpp
  lib/CodeGen/MachineCSE.cpp
  lib/CodeGen/MachineLICM.cpp
  lib/CodeGen/MachineRegisterInfo.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/CodeGen/PeepholeOptimizer.cpp
  lib/CodeGen/RegisterCoalescer.cpp

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