[PATCH] D14702: AVX512 : VMOVDDUP implementation.

[Igor Breger via llvm-commits]

igorb marked an inline comment as done.

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Comment at: lib/Target/X86/X86InstrSSE.td:5209
@@ -5208,4 +5208,3 @@
                     [(set VR256:$dst,
-                      (v4f64 (X86Movddup
-                              (scalar_to_vector (loadf64 addr:$src)))))]>,
+                      (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>,
                     Sched<[WriteLoad]>;
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RKSimon wrote:
> Please can you confirm that there is a test for this change?
Yes , I added shuffle_v4f64mem_0022 test case ( file vector-shuffle-256-v4.ll)
The previous lowering implementation was incorrect .The VMOVDDUP (VEX.256 ) instruction load 256bits and not 64bits.


Repository:
  rL LLVM

http://reviews.llvm.org/D14702