[PATCH] D14708: [mips] Disable code generation through FastISel for MIPS32R6.
Vasileios Kalintiris via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 16 09:07:41 PST 2015
This revision was automatically updated to reflect the committed changes.
Closed by commit rL253225: [mips] Disable code generation through FastISel for MIPS32R6. (authored by vkalintiris).
Changed prior to commit:
http://reviews.llvm.org/D14708?vs=40297&id=40298#toc
Repository:
rL LLVM
http://reviews.llvm.org/D14708
Files:
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
llvm/trunk/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
Index: llvm/trunk/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+
+; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+
+; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+
+; CHECK: FastISel missed terminator: ret i32 0
+
+define i32 @foo() {
+entry:
+ ret i32 0
+}
Index: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
@@ -192,10 +192,10 @@
TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
Context = &funcInfo.Fn->getContext();
+ bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
TargetSupported =
- ((TM.getRelocationModel() == Reloc::PIC_) &&
- ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
- (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
+ ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
+ (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
UnsupportedFPMode = Subtarget->isFP64bit();
}
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