[llvm] r253206 - Handle ARMv6KZ naming
Artyom Skrobov via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 16 06:05:32 PST 2015
Author: askrobov
Date: Mon Nov 16 08:05:32 2015
New Revision: 253206
URL: http://llvm.org/viewvc/llvm-project?rev=253206&view=rev
Log:
Handle ARMv6KZ naming
Summary:
* ARMv6KZ is the "canonical" name, given in the ARMARM
* ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM
* ARMv6ZK is a popular misspelling, which we should support as an alias.
The patch corrects the handling of the names.
Functional changes:
* ARMv6Z no longer treated as an architecture in its own right
* ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias
* arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K
* default ARMv6K CPU changed to arm1176j-s
Reviewers: rengolin, logan, compnerd
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D14568
Removed:
llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s
Modified:
llvm/trunk/include/llvm/Support/ARMTargetParser.def
llvm/trunk/lib/Support/TargetParser.cpp
llvm/trunk/lib/Support/Triple.cpp
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/trunk/test/MC/ARM/directive-arch-armv6z.s
llvm/trunk/unittests/ADT/TripleTest.cpp
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Mon Nov 16 08:05:32 2015
@@ -70,9 +70,7 @@ ARM_ARCH("armv6k", AK_ARMV6K, "6K", "v6k
FK_VFPV2, AEK_DSP)
ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
FK_NONE, AEK_DSP)
-ARM_ARCH("armv6z", AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ,
- FK_VFPV2, (AEK_SEC | AEK_DSP))
-ARM_ARCH("armv6zk", AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ,
+ARM_ARCH("armv6kz", AK_ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ,
FK_VFPV2, (AEK_SEC | AEK_DSP))
ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
FK_NONE, AEK_NONE)
@@ -171,13 +169,11 @@ ARM_CPU_NAME("arm1020e", AK_ARMV5TE, FK_
ARM_CPU_NAME("arm1022e", AK_ARMV5TE, FK_NONE, true, AEK_NONE)
ARM_CPU_NAME("arm926ej-s", AK_ARMV5TEJ, FK_NONE, true, AEK_NONE)
ARM_CPU_NAME("arm1136jf-s", AK_ARMV6, FK_VFPV2, true, AEK_NONE)
-ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, false, AEK_NONE)
-ARM_CPU_NAME("arm1176jz-s", AK_ARMV6K, FK_NONE, false, AEK_NONE)
+ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, true, AEK_NONE)
+ARM_CPU_NAME("arm1176jz-s", AK_ARMV6KZ, FK_NONE, false, AEK_NONE)
ARM_CPU_NAME("mpcore", AK_ARMV6K, FK_VFPV2, false, AEK_NONE)
ARM_CPU_NAME("mpcorenovfp", AK_ARMV6K, FK_NONE, false, AEK_NONE)
-ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6K, FK_VFPV2, true, AEK_NONE)
-ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6Z, FK_VFPV2, true, AEK_NONE)
-ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6ZK, FK_VFPV2, true, AEK_NONE)
+ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6KZ, FK_VFPV2, true, AEK_NONE)
ARM_CPU_NAME("arm1156t2-s", AK_ARMV6T2, FK_NONE, true, AEK_NONE)
ARM_CPU_NAME("arm1156t2f-s", AK_ARMV6T2, FK_VFPV2, false, AEK_NONE)
ARM_CPU_NAME("cortex-m0", AK_ARMV6M, FK_NONE, true, AEK_NONE)
Modified: llvm/trunk/lib/Support/TargetParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/lib/Support/TargetParser.cpp (original)
+++ llvm/trunk/lib/Support/TargetParser.cpp Mon Nov 16 08:05:32 2015
@@ -382,6 +382,7 @@ static StringRef getArchSynonym(StringRe
.Case("v5e", "v5te")
.Case("v6hl", "v6k")
.Cases("v6m", "v6sm", "v6s-m", "v6-m")
+ .Cases("v6z", "v6zk", "v6kz")
.Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
.Case("v7r", "v7-r")
.Case("v7m", "v7-m")
@@ -561,8 +562,7 @@ unsigned llvm::ARM::parseArchVersion(Str
case ARM::AK_ARMV6J:
case ARM::AK_ARMV6K:
case ARM::AK_ARMV6T2:
- case ARM::AK_ARMV6Z:
- case ARM::AK_ARMV6ZK:
+ case ARM::AK_ARMV6KZ:
case ARM::AK_ARMV6M:
return 6;
case ARM::AK_ARMV7A:
Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Mon Nov 16 08:05:32 2015
@@ -497,10 +497,9 @@ static Triple::SubArchType parseSubArch(
return Triple::ARMSubArch_v5te;
case ARM::AK_ARMV6:
case ARM::AK_ARMV6J:
- case ARM::AK_ARMV6Z:
return Triple::ARMSubArch_v6;
case ARM::AK_ARMV6K:
- case ARM::AK_ARMV6ZK:
+ case ARM::AK_ARMV6KZ:
return Triple::ARMSubArch_v6k;
case ARM::AK_ARMV6T2:
return Triple::ARMSubArch_v6t2;
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Mon Nov 16 08:05:32 2015
@@ -289,7 +289,7 @@ def ARMv6t2 : Architecture<"armv6t2",
def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
-def ARMv6z : Architecture<"armv6z", "ARMv6z", [HasV6KOps,
+def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
FeatureTrustZone]>;
def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
@@ -413,8 +413,8 @@ def : Processor<"cortex-m0plus", ARMV
def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
-def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6z]>;
-def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6z,
+def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
+def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
FeatureVFP2,
FeatureHasSlowFPVMLx]>;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Nov 16 08:05:32 2015
@@ -51,7 +51,7 @@ protected:
};
enum ARMArchEnum {
ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
- ARMv5tej, ARMv6, ARMv6k, ARMv6z, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
+ ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
ARMv7m, ARMv7em, ARMv8a, ARMv81a
};
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp Mon Nov 16 08:05:32 2015
@@ -719,8 +719,7 @@ void ARMTargetELFStreamer::emitArchDefau
break;
case ARM::AK_ARMV6K:
- case ARM::AK_ARMV6Z:
- case ARM::AK_ARMV6ZK:
+ case ARM::AK_ARMV6KZ:
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(Virtualization_use, AllowTZ, false);
Modified: llvm/trunk/test/MC/ARM/directive-arch-armv6z.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-arch-armv6z.s?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv6z.s (original)
+++ llvm/trunk/test/MC/ARM/directive-arch-armv6z.s Mon Nov 16 08:05:32 2015
@@ -11,12 +11,12 @@
.syntax unified
.arch armv6z
-@ CHECK-ASM: .arch armv6z
+@ CHECK-ASM: .arch armv6kz
@ CHECK-ATTR: FileAttributes {
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: CPU_name
-@ CHECK-ATTR: Value: 6Z
+@ CHECK-ATTR: Value: 6KZ
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: CPU_arch
Removed: llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s?rev=253205&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s (original)
+++ llvm/trunk/test/MC/ARM/directive-arch-armv6zk.s (removed)
@@ -1,38 +0,0 @@
-@ Test the .arch directive for armv6zk
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv6zk architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN: | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
-
- .syntax unified
- .arch armv6zk
-
-@ CHECK-ASM: .arch armv6zk
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_name
-@ CHECK-ATTR: Value: 6ZK
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: ARM v6KZ
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: ARM_ISA_use
-@ CHECK-ATTR: Description: Permitted
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: THUMB_ISA_use
-@ CHECK-ATTR: Description: Thumb-1
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: Virtualization_use
-@ CHECK-ATTR: Description: TrustZone
-@ CHECK-ATTR: }
-@ CHECK-ATTR: }
-
Modified: llvm/trunk/unittests/ADT/TripleTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/TripleTest.cpp?rev=253206&r1=253205&r2=253206&view=diff
==============================================================================
--- llvm/trunk/unittests/ADT/TripleTest.cpp (original)
+++ llvm/trunk/unittests/ADT/TripleTest.cpp Mon Nov 16 08:05:32 2015
@@ -856,6 +856,10 @@ TEST(TripleTest, getARMCPUForArch) {
}
{
llvm::Triple Triple("armv6k-unknown-eabi");
+ EXPECT_EQ("arm1176j-s", Triple.getARMCPUForArch());
+ }
+ {
+ llvm::Triple Triple("armv6kz-unknown-eabi");
EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
}
{
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