[PATCH] D14489: [AArch64] Applying load pair optimization for volatile load/store

[Tim Northover via llvm-commits]

t.p.northover added a comment.

> I believe what actually happens is that Device-nGnRnE is completely ordered under all circumstances, Device-nGnEE is ordered within itself but can be reordered with accesses to Normal memory, and the others are even weaker.


Oops, this seems wrong on a more thorough reading. I don't think nGnRnE is actually that strong, though I still think the description of nGnRE is probably roughly right and prevents us from reordering volatiles. E.g. on the Reordering attribute:

> For all memory types with the non-Reordering attribute, the order of memory accesses arriving at a single peripheral of IMPLEMENTATION DEFINED size, as defined by the peripheral, must be the same order that occurs in a simple sequential execution of the program. That is, the accesses appear in program order.



http://reviews.llvm.org/D14489